Timing Performance of Nanometer Digital Circuits Under Process Variations

Description

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability. Front Matter ....Pages i-xviii Introduction (Victor Champac, Jose Garcia Gervacio)....Pages 1-17 Mathematical Fundamentals (Victor Champac, Jose Garcia Gervacio)....Pages 19-39 Process Variations (Victor Champac, Jose Garcia Gervacio)....Pages 41-69 Gate Delay Under Process Variations (Victor Champac, Jose Garcia Gervacio)....Pages 71-95 Path Delay Under Process Variations (Victor Champac, Jose Garcia Gervacio)....Pages 97-118 Circuit Analysis Under Process Variations (Victor Champac, Jose Garcia Gervacio)....Pages 119-141 Designing with FinFETs and Process Variation Impact (Victor Champac, Jose Garcia Gervacio)....Pages 143-163 Back Matter ....Pages 165-185