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Laung-Terng Wang

System-on-Chip Test Architectures. Nanometer Design for Testability

System-on-Chip Test Architectures. Nanometer Design for Testability

2008 · ENGLISH · PDF

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Power-Aware Testing and Test Strategies for Low Power Devices

Power-Aware Testing and Test Strategies for Low Power Devices

2010 · ENGLISH · PDF

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Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)

Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)

2009 · ENGLISH · PDF

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Power-Aware Testing and Test Strategies for Low Power Devices

Power-Aware Testing and Test Strategies for Low Power Devices

2010 · ENGLISH · PDF

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VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

2006 · ENGLISH · PDF

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VLSI Test Principles and Architectures: Design for Testability

VLSI Test Principles and Architectures: Design for Testability

2006 · ENGLISH · PDF

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VLSI Test Principles and Architectures: Design for Testability

VLSI Test Principles and Architectures: Design for Testability

2006 · ENGLISH · PDF

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System-on-Chip Test Architectures: Nanometer Design for Testability (Systems on Silicon)

System-on-Chip Test Architectures: Nanometer Design for Testability (Systems on Silicon)

2007 · ENGLISH · PDF

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