ENGLISH

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

By Krishnendu Chakrabarty (auth.) , Brandon Noia

Book information

Publisher
Springer International Publishing
Year
2014
ISBN
978-3-319-02377-9, 978-3-319-02378-6
DOI
10.1007/978-3-319-02378-6
Language
english
Format
PDF
Filesize
7 MB (6911767 bytes)
Edition
1
Pages
245\260
Time added
2014-01-18 08:00:00
Circuits and Systems; Processor Architectures; Sem

Description

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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