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John P. Hayes (auth.)

Design, Analysis and Test of Logic Circuits Under Uncertainty

Design, Analysis and Test of Logic Circuits Under Uncertainty

2013 · ENGLISH · PDF

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Design, Analysis and Test of Logic Circuits Under Uncertainty

Design, Analysis and Test of Logic Circuits Under Uncertainty

2013 · ENGLISH · PDF

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Layout Minimization of CMOS Cells

Layout Minimization of CMOS Cells

1992 · ENGLISH · PDF

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Hierarchical Modeling for VLSI Circuit Testing

Hierarchical Modeling for VLSI Circuit Testing

1990 · ENGLISH · PDF

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