ENGLISH

High Performance Embedded Architectures and Compilers: Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008. Proceedings

By Mateo Valero , Jesús Labarta (auth.) , Per Stenström , Michel Dubois , Manolis Katevenis , Rajiv Gupta , Theo Ungerer (eds.)

Book information

Publisher
Springer-Verlag Berlin Heidelberg
Year
2008
ISBN
978-3-540-77559-1, 978-3-540-77560-7
DOI
10.1007/978-3-540-77560-7
Language
english
Format
PDF
Filesize
9 MB (9917515 bytes)
Series
Lecture Notes in Computer Science 4917 Theoretical Computer Science and General Issues
Edition
1
Pages
400\399
Time added
2014-01-18 08:00:00
Arithmetic and Logic Structures; Processor ArchiteCompilersInterpreters

Description

This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized into topical sections on a number of key subjects in the field, including multithreaded and multicore processors, reconfigurable ASIP, and compiler optimizations. Also covered are industrial processors and application parallelization, power-aware techniques, and high-performance processors. The book also contains material on the collection and analysis of profiles as well as optimizing memory performance.

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