Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)

Description

This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. Front Matter....Pages i-xxvii Introduction....Pages 1-8 Synthesis Basics....Pages 9-15 Timing Analysis and Constraints....Pages 17-33 SDC Extensions Through Tcl....Pages 35-46 Clocks....Pages 47-55 Generated Clocks....Pages 57-69 Clock Groups....Pages 71-80 Other Clock Characteristics....Pages 81-94 Port Delays....Pages 95-115 Completing Port Constraints....Pages 117-130 False Paths....Pages 131-144 Multi Cycle Paths....Pages 145-155 Combinational Paths....Pages 157-166 Modal Analysis....Pages 167-175 Managing Your Constraints....Pages 177-192 Miscellaneous SDC Commands....Pages 193-207 XDC: Xilinx Extensions to SDC....Pages 209-218 Back Matter....Pages 219-226