ENGLISH

Designing Reliable and Efficient Networks on Chips

By Dr. Srinivasan Murali (auth.)

Book information

Publisher
Springer Netherlands
Year
2009
ISBN
978-1-4020-9756-0, 978-1-4020-9757-7
DOI
10.1007/978-1-4020-9757-7
Language
english
Format
PDF
Filesize
5 MB (5588597 bytes)
Series
Lecture Notes in Electrical Engineering 34
Edition
1
Pages
198\199
Orientation
yes
Scanned
yes
Time added
2013-08-01 04:00:00
Circuits and Systems; Processor Architectures

Description

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

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