System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

Description

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. · Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; · Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; · Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; · Explains each concept in a step-by-step fashion and applies it to a practical real life example; · Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book. Front Matter ....Pages i-xxxix Introduction (Ashok B. Mehta)....Pages 1-8 Front Matter ....Pages 9-9 System Verilog Assertions (Ashok B. Mehta)....Pages 11-31 Sequential Domain Coverage (“Cover” Property and “Cover” Sequence) (Ashok B. Mehta)....Pages 33-36 Conventions Used in the Book (Ashok B. Mehta)....Pages 37-38 Immediate Assertions (Ashok B. Mehta)....Pages 39-47 Concurrent Assertions: Basics (Ashok B. Mehta)....Pages 49-84 Sampled Value Functions (Ashok B. Mehta)....Pages 85-98 Operators (Ashok B. Mehta)....Pages 99-161 System Functions and Tasks (Ashok B. Mehta)....Pages 163-170 Multiple Clocks (Ashok B. Mehta)....Pages 171-182 Local Variables (Ashok B. Mehta)....Pages 183-196 Recursive Property (Ashok B. Mehta)....Pages 197-202 Endpoint of a Sequence (.triggered and .matched) (Ashok B. Mehta)....Pages 203-216 “expect” (Ashok B. Mehta)....Pages 217-220 “assume” and “restrict” for Simulation and Formal (Static Functional) Verification (Ashok B. Mehta)....Pages 221-225 Clock Domain Crossing (CDC) Verification Using Assertions (Ashok B. Mehta)....Pages 227-233 Important Topics (Ashok B. Mehta)....Pages 235-267 Asynchronous FIFO Assertions (Ashok B. Mehta)....Pages 269-277 Asynchronous Assertions (Ashok B. Mehta)....Pages 279-284 IEEE-1800-2009/2012 Features (Ashok B. Mehta)....Pages 285-323 “let” Declarations (Ashok B. Mehta)....Pages 325-333 Checkers (Ashok B. Mehta)....Pages 335-352 SystemVerilog Assertions LABs (Ashok B. Mehta)....Pages 353-395 System Verilog Assertions: LAB Answers (Ashok B. Mehta)....Pages 397-417 Front Matter ....Pages 419-419 Functional Coverage (Ashok B. Mehta)....Pages 421-430 Functional Coverage: Language Features (Ashok B. Mehta)....Pages 431-482 Performance Implications of Coverage Methodology (Ashok B. Mehta)....Pages 483-492 Coverage Options (Ashok B. Mehta)....Pages 493-501 Back Matter ....Pages 503-507