ENGLISH

VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design

By Prof. Dr. Ulrich Golze (auth.)

Book information

Publisher
Springer-Verlag Berlin Heidelberg
Year
1996
ISBN
978-3-642-64650-8, 978-3-642-61001-1
DOI
10.1007/978-3-642-61001-1
Language
english
Format
PDF
Filesize
16 MB (16674397 bytes)
Edition
1
Pages
360\363
Time added
2014-01-18 08:00:00
InstrumentationLogic Design; Electronics and Microelectronics

Description

This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.

Similar books