From Algorithms to Hardware Architectures: Using Digital Radios as a Design Example

Description

This book uses digital radios as a challenging design example, generalized to bridge a typical gap between designers who work on algorithms and those who work to implement those algorithms on silicon. The author shows how such a complex system can be moved from high-level characterization to a form that is ready for hardware implementation. Along the way, readers learn a lot about how algorithm designers can benefit from knowing the hardware they target and how hardware designers can benefit from a familiarity with the algorithm. The book shows how a high-level description of an algorithm can be migrated to a fixed-point block diagram with a well-defined cycle accurate architecture and a fully documented controller. This can significantly reduce the length of the hardware design cycle and can improve its outcomes. Ultimately, the book presents an explicit design flow that bridges the gap between algorithm design and hardware design. Provides a guide to baseband radio design for Wi-Fi and cellular systems, from an implementation-focused, perspective;Explains how arithmetic is moved to hardware and what the cost of each operation is in terms of delay, area and power;Enables strategic architectural decisions based on the algorithm, available processing units and design requirements. Preface Contents List of Abbreviations Chapter 1: What Is a Radio? 1.1 Our Most Valuable Resource, the Radio Spectrum 1.2 Getting People Out of Each Other´s Way, the Layer Model 1.3 A Signal as It Really Is, Radio Frequency Signals 1.4 Avoiding a Fight Over the Channel, Medium Access Control (MAC) 1.5 Making Ones and Zeros More Than Ones and Zeros, the Baseband Radio Chapter 2: Basics of Baseband Radios 2.1 The Case for Complex Numbers, Signals in Baseband and Passband 2.2 Noise and Signals, Random Variables, and Stochastic Processes, Mathematics 2.3 Receiver and Transmitter Architecture 2.4 Why MIMO-OFDM? 2.5 Packet-Based Communication 2.6 The Quest for More Bits, Evolution of Wi-Fi 2.7 Measuring Goodness, Quality Metrics: SNR, BER, Throughput, Energy, and Goodput Chapter 3: Multiplications to Multipliers: Performing Arithmetic in Hardware 3.1 Numbers on Computers and Numbers on Dedicated Hardware: Fixed-Point Registers 3.2 Modeling Fixed-Point Number Generation 3.3 Fixed-Point Addition 3.4 Fixed-Point Multiplication and Managing Wordlength Growth 3.5 Processing Complex Numbers 3.6 Processing Vectors and Matrices 3.7 Implementation Platforms 3.8 Hardware Architectures 3.9 Cost and Performance of Arithmetic Chapter 4: The Wireless Channel 4.1 Partitioning Wireless Channel Effects 4.2 Additive White Gaussian Noise (AWGN), a Fact of Nature 4.3 Single-Path Rayleigh Fading, Reflectors in the Environment 4.4 Crowded Environments, Multipath (Frequency-Selective) Channels 4.5 The Cost of Distance, Path Loss 4.6 Doppler, Channels That Do Not Stand Still 4.7 Having a Line of Sight, Rician Fading 4.8 Large Obstacles to Communication, Shadowing 4.9 How to Determine the Type of Channel Chapter 5: Baseband Modulation 5.1 Sending a Message Over the Air 5.2 The Missing Dimension, QPSK 5.3 Phase-Shift Keying and the Economy of Empty Spaces 5.4 Quadrature Amplitude Modulation, Trading Efficiency for BER 5.5 Visualizing Channel Effects Through Constellation Diagrams 5.6 How to Do Hard Decision Decoding, the Maximum Likelihood Result 5.7 Soft Decisions 5.8 Channel Capacity, the Best Anyone Can Do Chapter 6: Forward Error Correction 6.1 Why Do Channel Coding 6.2 Channel Encoding and Decoding in Wi-Fi 6.3 Transmitter Architecture Revisited 6.4 Puncturing and Depuncturing, Obtaining Multiple Coding Rates with the Same Decoder 6.5 Trellis Derivation, Visualizing the Encoder Message 6.6 Maximum Likelihood Decoding, the Best Anyone Can Do 6.7 The Viterbi Algorithm, Taking a Calculated Hit 6.8 Breaking Down a Complicated Solution, Partitioning the Viterbi Algorithm 6.9 The Branch Metric Unit (BMU) 6.10 The Path Metric Unit (PMU) 6.11 The Traceback Unit 6.12 Bringing It All Together, Building the Viterbi Decoder 6.13 Frequency Interleaving and Deinterleaving, Allowing Viterbi to Handle Faded Channels Chapter 7: OFDM 7.1 Multipath and Frequency Selectivity: The Conundrum of Equalization 7.2 Narrowband Transmission and Maintaining Throughput 7.3 OFDM: The Good and the Ugly 7.4 Avoiding the Use of Multiple Correlators, OFDM in 802.11n 7.5 Time-Domain to Frequency-Domain Transforms 7.6 FFT as an Implementation of DFT 7.7 Decimation in Time 7.8 Decimation in Frequency 7.9 Higher Radix FFT 7.10 What Does the Guard Interval Really Contain? 7.11 Using the Same Hardware for IFFT and FFT 7.12 Bit Reversal 7.13 Populating the OFDM Symbol 7.14 MCS, Useful Throughput, and Cognitive Radios 7.15 We Can Finally Look at Everything in the Receiver Chapter 8: Algorithm to Hardware: FFT as a Case Study 8.1 Design Adaptation Flow 8.2 Components of a Digital Architecture 8.2.1 The Datapath 8.2.2 Processing Units (PUs) 8.2.3 Storage 8.2.4 Flow Control 8.2.5 Controller 8.2.6 Address Generators 8.3 16-Point FFT: The SFG as ``the Algorithm´´ 8.4 Prepare Your Block Diagram and Isolate Processing Units 8.5 Perform Fixed-Point Analysis and Determine Bus Sizes 8.6 Try Out (and Immediately Hate) the Direct Implementation 8.7 What Can You Do If the Direct Implementation Has a Throughput Deficit: Parallelism and Pipelining 8.8 Calculating Needed Throughput: Application and Implementation 8.9 Time-Sharing Processing Units 8.10 Resolving Memory Bandwidth Limitations 8.11 Think About Your Controller 8.12 Hard-Coded Controllers: Finite State Machine 8.13 Instruction-Driven Controllers: Flexibility and Programmability 8.13.1 Fully Expanded Instruction 8.13.2 Coded Instructions 8.13.3 Introducing Absolute Looping 8.13.4 Introducing Conditions 8.13.5 The Ultimate Result 8.14 Time-Sharing Revisited: Reconfigurable Hardware and Accelerators 8.15 Which Architecture Is ``Best´´? Chapter 9: MIMO 9.1 What Can You Do with Multiple Antennas? 9.2 Receiver Diversity 9.3 Transmitter Diversity 9.4 Beamforming 9.5 Spatial Multiplexing and True MIMO 9.6 Zero Forcing and SIC 9.7 MMSE 9.8 Maximum Likelihood Decoding 9.9 QR Decomposition for Matrix Inversion 9.10 Decoding by Using the Singular Value Decomposition (SVD) 9.11 Givens Rotations 9.12 Complex Givens Rotations and Channel Inversion 9.13 Sphere Decoding 9.14 Two-Sided Jacobi for Singular Value Decomposition 9.15 Comparison of MIMO Decoding Algorithms and Algorithm as Part of Cognition Chapter 10: Advanced Issues in Migrating to Hardware: MIMO Decoders as Case Studies 10.1 Naïve Implementation of Unitary Transformations 10.2 CORDIC 10.3 Vectoring CORDIC 10.4 Rotation CORDIC 10.5 Iterations, Wordlength, and Hardware Implementation of CORDIC 10.6 CORDIC for Givens Rotations 10.7 Super CORDIC: Handling Complex Numbers 10.8 CORDIC for QR Decomposition and Systolic Arrays 10.9 Collapsed Arrays and Time-Sharing: Accelerators as an Approach to Implementation 10.10 Generic Use of CORDIC and Two-Sided Jacobi in Hardware 10.11 Is a Naïve Implementation Always Bad? 10.12 Clocks, Architectures, Speed, Throughput, and Latency: Sorting Through the Lingo Chapter 11: Synchronization 11.1 802.11n Packet Structure 11.2 The Legacy Header 11.2.1 L-STF 11.2.2 L-LTF 11.2.3 L-SIG 11.3 The High Throughput Header 11.3.1 HT-SIG1 and HT-SIG2 11.3.2 HT-STF 11.3.3 HT-LTF 11.4 Scrambling, Padding, and CRC 11.5 MIMO Channel Estimation: Easier Than You Think 11.6 Frequency Offset Estimation and Correction: What OFDM Would Die Without 11.7 Timing Offset Estimation and Correction: What OFDM Does Not Really Care About 11.8 Packet Edge Detection: Waking the Receiver Chapter 12: Cellular Radios 12.1 What Does a Cellular System Look Like? 12.2 Are Wi-Fi and Cellular Really That Different? Yes! 12.3 Downlink Frame, PRB, and Bandwidth Allocation 12.4 Pilots and MIMO Decoding in Cellular Systems 12.5 OFDMA and SC-FDMA: Using the Asymmetric Links to Our Advantage 12.6 LTE to 5G: Things That Change and Things That Do Not 12.7 MU-MIMO: The Future Index