Handbook Of Digital CMOS Technology, Circuits, And Systems

Description

This book provides a comprehensive reference for everything that has to do with digital circuits. The author focuses equally on all levels of abstraction. He tells a bottom-up story from the physics level to the finished product level. The aim is to provide a full account of the experience of designing, fabricating, understanding, and testing a microchip. The content is structured to be very accessible and self-contained, allowing readers with diverse backgrounds to read as much or as little of the book as needed. Beyond a basic foundation of mathematics and physics, the book makes no assumptions about prior knowledge. This allows someone new to the field to read the book from the beginning. It also means that someone using the book as a reference will be able to answer their questions without referring to any external sources. There’s Something About Electronics......Page 6 Analog Circuits......Page 7 Digital Circuits......Page 8 Mixed-Signal Circuits......Page 9 It’s an Abstract Art......Page 10 What is This All About?......Page 12 How to Use This Book......Page 17 Assumptions, Simplifications, Accuracy, and Managing to Do Anything......Page 19 The Story as It Is Told......Page 20 Contents......Page 23 1.1 The Band Model......Page 27 1.2 Intrinsic Silicon......Page 32 1.3 Band Model with Doping......Page 36 1.4 Extrinsic Silicon......Page 40 1.5 Drift......Page 43 1.6 Diffusion......Page 47 1.7 Forming a Homojunction......Page 49 1.8 PN Junction in Equilibrium......Page 52 1.9 Junction Capacitance......Page 55 1.10 Forward and Reverse Bias......Page 57 1.11 Minority Carrier Injection......Page 59 1.12 Forward-Biased PN Junction Current......Page 61 1.13 Bipolar Junction Transistor......Page 67 1.14 Materials Interfaces......Page 75 1.15 MOS Capacitor Preliminaries......Page 81 1.16 Modes of the MOS Capacitor......Page 84 1.17 MOS Capacitor Characteristics......Page 91 1.18 MOSFET Linear Regime......Page 93 1.19 MOSFET Saturation Regime......Page 94 1.20 Body Effect......Page 100 1.21 Channel Length Modulation......Page 103 2.1 PMOS......Page 106 2.2 Regions of the MOSFET......Page 107 2.4 Abandoning BJT......Page 110 2.5 Scaling MOSFET......Page 113 2.6 What is a Logic Family......Page 115 2.7 Resistive Load Inverter......Page 118 2.8 Open-Circuited Transistor......Page 120 2.9 Enhancement Load Inverter......Page 121 2.10 Enhancement Load VTC......Page 122 2.11 Static Power......Page 123 2.12 NAND and NOR Enhancement Load......Page 124 2.13 Random Logic in Enhancement Load......Page 128 2.14 Depletion Load Logic......Page 129 2.15 Pseudo-NMOS Logic......Page 131 2.16 Limitations of Ratioed Logic......Page 132 3.1 Basics of the CMOS Inverter......Page 135 3.2 CMOS VTC......Page 136 3.3 Preliminaries of Delay......Page 140 3.4 MOS Capacitance and Resistance......Page 144 3.5 Simplified Delay Model......Page 147 3.6 Non-static Power......Page 149 3.7 CMOS NAND and NOR......Page 152 3.8 CMOS Complex Logic......Page 154 3.9 Sizing, Delay, and Area......Page 159 3.10 Supply and Width Scaling......Page 165 3.11 Limitations of CMOS......Page 166 4.2 Sizing an Inverter Chain......Page 168 4.3 Gates Versus Inverters: Preliminaries......Page 171 4.4 Normalizing Gate Intrinsic Delay......Page 172 4.5 Normalizing Gate External Delay......Page 173 4.6 Architecture, Inputs, and Effort......Page 175 4.7 Optimal Sizing in a Logic Chain......Page 176 4.8 Logical Effort for Multiple Inputs......Page 179 5.1 High-Impedance Nodes......Page 180 5.2 Dynamic CMOS and Why it is Great......Page 181 5.4 Leakage in Dynamic Logic......Page 185 5.5 Charge Sharing......Page 190 5.6 Cascading Dynamic Logic......Page 194 5.7 Logical Effort in Dynamic Gates......Page 198 6.1 Sequential Versus Combinational......Page 200 6.2 Latches, Registers, and Timing......Page 203 6.3 The Static Register......Page 204 6.4 Dynamic Registers......Page 210 6.5 Imperfect Clocks and Hold-Time......Page 211 6.6 Pipelines, Critical Path, and Slack......Page 215 6.7 Managing Power in a Pipeline......Page 222 6.8 Examples on Pipelining......Page 228 6.9 Impact of Variations......Page 236 7.1 Setting and Location......Page 239 7.2 Photolithography Iteration......Page 241 7.3 Account of Materials......Page 243 7.4 Wafer Fabrication......Page 245 7.5 Operations and Equipment......Page 248 7.6 Locos......Page 259 7.7 Advanced Issues in CMOS Processing......Page 269 7.8 Account of Layers......Page 293 8.1 What Is a Layout......Page 296 8.2 Stick Diagrams......Page 297 8.3 Standard Cells......Page 301 8.4 Design Rules: Foundations......Page 309 8.5 Design Rules—Sample......Page 313 8.6 Fixed-Point Simulation......Page 319 8.7 Physical Design......Page 324 8.8 FPGAs......Page 333 9.1 Design Philosophy......Page 338 9.3 IEEE Library and std_logic......Page 340 9.4 Types, Attributes, and Operators......Page 343 9.6 Structural Connections......Page 348 9.7 Generics and Constants......Page 356 9.9 The Process Statement......Page 363 9.10 Signals and Variables......Page 366 9.11 Selection in a Process......Page 368 9.12 Latches and Implicit Latches......Page 369 9.13 Registers and Pipelines......Page 378 9.14 Memories......Page 386 9.15 Counters......Page 390 9.16 State Machines......Page 394 9.17 Testbenches—Preliminaries......Page 400 9.18 Functions and Procedures......Page 402 9.19 Wait, Assertions, and Loops......Page 408 9.20 File I/Os......Page 415 9.21 Packages and Configurations......Page 422 9.22 Good Design Practices......Page 426 10.1 Steep Retrograde Body Effect......Page 431 10.2 Velocity Saturation......Page 432 10.3 MOSFET Leakage......Page 436 10.4 DIBL......Page 442 10.5 MOSFET Structures for DIBL......Page 447 10.6 Miscellaneous Scaling Effects......Page 450 10.7 Impacts on CMOS......Page 455 11.1 Binary Addition and Full Adders......Page 459 11.2 Ripple Carry Adder......Page 461 11.3 Generate—Propagate Logic......Page 462 11.4 Carry-Save and Bypass Adders......Page 465 11.5 Lookahead Addition......Page 469 11.6 Group Generates and Propagates......Page 471 11.7 Parallel Prefix Adders......Page 473 11.8 Binary Multiplication......Page 476 11.9 Array Multipliers......Page 477 11.10 Wallace and DADDA Multipliers......Page 479 11.11 Booth Multiplication......Page 484 12.1 Architectures and Definitions......Page 490 12.2 NOR ROM Arrays......Page 493 12.3 NAND ROM Arrays......Page 498 12.4 NVMs......Page 501 12.5 SRAM Cell......Page 511 12.6 Sense Amplifiers......Page 515 12.7 SRAM Timing......Page 519 12.8 DRAM Cells......Page 523 12.9 Decoders and Buffers......Page 529 13.1 Basics......Page 538 13.2 Lumped C Wires......Page 541 13.3 Silicon Wires......Page 543 13.4 Scaling Wires......Page 544 13.5 Interchip Communication......Page 546 13.6 Supply and Ground......Page 552 13.7 Clock Networks......Page 555 13.8 Metastability......Page 559 13.9 Synchronization......Page 565 14.1 Fundamentals of Testing......Page 570 14.2 Logical Hazards......Page 578 14.3 Stuck-at Fault Model......Page 586 14.4 Scan Paths......Page 590 14.5 Built in Self-test......Page 595 14.6 IC Packaging and Boundary Scan......Page 599 14.7 Testing Memories......Page 605 14.8 Reliability......Page 608 Glossary......Page 611 Index......Page 651