Computer Architecture: ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers

Description

This book constitutes the thoroughly refereed post-conference proceedings of the workshops held at the 37th International Symposium on Computer Architecture, ISCA 2010, in Saint-Malo, France, in June 2010. The 28 revised full papers presented were carefully reviewed and selected from the lectures given at 5 of these workshops. The papers address topics ranging from novel memory architectures to emerging application design and performance analysis and encompassed the following workshops: A4MMC, applications for multi- and many-cores; AMAS-BT, 3rd workshop on architectural and micro-architectural support for binary translation; EAMA, the 3rd Workshop for emerging applications and many-core architectures; WEED, 2nd Workshop on energy efficient design, as well as WIOSCA, the annual workshop on the interaction between operating systems and computer architecture. Front Matter....Pages - Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine....Pages 1-12 Performance Impact of Task Mapping on the Cell BE Multicore Processor....Pages 13-23 Parallelization Strategy for CELL TV....Pages 24-27 Towards User Transparent Parallel Multimedia Computing on GPU-Clusters....Pages 28-39 Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture....Pages 40-51 On the Use of Small 2D Convolutions on GPUs....Pages 52-64 Can Manycores Support the Memory Requirements of Scientific Applications?....Pages 65-76 Parallelizing an Index Generator for Desktop Search....Pages 77-85 Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks....Pages 86-98 Trace Execution Automata in Dynamic Binary Translation....Pages 99-116 ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation....Pages 117-138 Parallelization of Particle Filter Algorithms....Pages 139-149 What Kinds of Applications Can Benefit from Transactional Memory?....Pages 150-160 Characteristics of Workloads Using the Pipeline Programming Model....Pages 161-171 The Search for Energy-Efficient Building Blocks for the Data Center....Pages 172-182 KnightShift: Shifting the I/O Burden in Datacenters to Management Processor for Energy Efficiency....Pages 183-197 Guarded Power Gating in a Multi-core Setting....Pages 198-210 Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors....Pages 211-221 Achieving Power-Efficiency in Clusters without Distributed File System Complexity....Pages 222-232 What Computer Architects Need to Know about Memory Throttling....Pages 233-242 Predictive Power Management for Multi-core Processors....Pages 243-255 IOMMU: Strategies for Mitigating the IOTLB Bottleneck....Pages 256-274 Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality....Pages 275-292 Performance Characteristics of Explicit Superpage Support....Pages 293-310 Interfacing Operating Systems and Polymorphic Computing Platforms Based on the MOLEN Programming Paradigm....Pages 311-323 Extrinsic and Intrinsic Text Cloning....Pages 324-340 A Case for Coordinated Resource Management in Heterogeneous Multicore Platforms....Pages 341-356 Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors....Pages 357-375 Back Matter....Pages -