Introduction to Logic Design

Description

Front Cover Title Page Copyright Page Preface Brief Contents CONTENTS CHAPTER 1: Introduction 1.1 Logic Design 1.1.1 The Laboratory 1.2 A Brief Review of Number Systems 1.2.1 Hexadecimal 1.2.2 Binary Addition 1.2.3 Signed Numbers 1.2.4 Binary Subtraction 1.2.5 Binary Coded Decimal (BCD) 1.2.6 Other Codes 1.3 Solved Problems 1.4 Exercises 1.5 Chapter 1 Test CHAPTER 2: Combinational Systems 2.1 The Design Process for CombinationalSystems 2.1.1 Don’t Care Conditions 2.1.2 The Development of Truth Tables 2.2 Switching Algebra 2.2.1 Definition of Switching Algebra 2.2.2 Basic Properties of Switching Algebra 2.2.3 Manipulation of Algebraic Functions 2.3 Implementation of Functions with AND, OR,and NOT Gates 2.4 The Complement 2.5 From the Truth Table to Algebraic Expressions 2.6 NAND, NOR, and Exclusive-OR Gates 2.7 Simplification of Algebraic Expressions 2.8 Manipulation of Algebraic Functions andNAND Gate Implementations 2.9 A More General Boolean Algeb 2.10 Solved Problems 2.11 Exercises 2.12 Chapter 2 Test CHAPTER 3: The Karnaugh Map 3.1 Introduction to the Karnaugh Map 3.2 Minimum Sum of Product Expressions Usingthe Karnaugh Map 3.3 Don’t Cares 3.4 Product of Sums 3.5 Five- and Six-Variable Maps 3.6 Multiple Output Problems 3.7 Solved Problems 3.8 Exercises 3.9 Chapter 3 Test CHAPTER 4: Function Minimization Algorithms 4.1 Quine-McCluskey Methodfor One Output 4.2 Iterated Consensus for One Output 4.3 Prime Implicant Tables for One Output 4.4 Quine-McCluskey for Multiple Output Problems 4.5 Iterated Consensus for Multiple OutputProblems 4.6 Prime Implicant Tables for Multiple OutputProblems 4.7 Solved Problems 4.8 Exercises 4.9 Chapter 4 Test CHAPTER 5: Designing Combinational Systems 5.1 Iterative Systems 5.1.1 Delay in CombinationalLogic Circuits 5.1.2 Adders 5.1.3 Subtractors and Adder/Subtractors 5.1.4 Comparators 5.2 Binary Decoders 5.3 Encoders and Priority Encoders 5.4 Multiplexers and Demultiplexers 5.5 Three-State Gate 5.6 Gate Arrays—ROMs, PLAs,and PALs 5.6.1 Designing with Read-OnlyMemorie 5.6.2 Designing with Programmable LogicArrays 5.6.3 Designing with Programmable ArrayLogic 5.7 Testing and Simulation of Combinational Systems 5.7.1 An Introduction to Verilog 5.8 Larger Examples 5.8.1 A One-Digit Decimal Adder 5.8.2 A Driver for a Seven-Segment Display 5.9 Solved Problems 5.10 Exercises 5.11 Chapter 5 Test CHAPTER 6: Analysis of Sequential Systems 6.1 State Tables and Diagrams 6.2 Latches 6.3 Flip Flops 6.4 Analysis of Sequential Systems 6.5 Solved Problems 6.6 Exercises 6.7 Chapter 6 Test CHAPTER 7: The Design of Sequential Systems 7.1 Flip Flop Design Techniques 7.2 The Design of Synchronous Counters 7.3 Design of Asynchronous Counters 7.5 Solved Problems 7.6 Exercises 7.7 Chapter 7 Test CHAPTER 8: Solving Larger Sequential Problems 8.1 Shift Registers 8.2 Counters 8.3 Programmable Logic Devices (PLDs) 8.4 Design Using ASM Diagrams 8.5 One-Hot Encoding 8.6 Verilog for Sequential Systems 8.7 Design of a Very Simple Computer 8.8 Other Complex Examples 8.9 Solved Problems 8.10 Exercises 8.11 Chapter 8 Test CHAPTER 9: Simplification of Sequential Circuits 9.1 A Tabular Method for State Reduction 9.2 Partitions 9.2.1 Properties of Partitions 9.2.2 Finding SP Partitions 9.3 State Reduction using Partitions 9.4 Choosing a State Assignment 9.5 Solved Problems 9.6 Exercises 9.7 Chapter 9 Test APPENDICES A: Relating the Algebrato the Karnaugh Map B: Answers to Selected Exercises C: Chapter Test Answers D: Laboratory Experiments D.1 Hardware Logic Lab D.2 WinBreadboard™ andMacBreadboard™ D.3 Introduction to LogicWorks D.4 A Set of Logic Design Experiments D.4.1 Experiments Based on Chapter 2Material D.4.2 Experiments Based on Chapter 5Material D.4.3 Experiments Based on Chapter 6Material D.4.4 Experiments Based on Chapter 7Material D.4.5 Experiments Based on Chapter 8Material D.5 Layout of Chips Referenced in the Textand Experiments E: Complete Examples INDEX errata Quick Reference Material Flip Flops Summary of Properties of Switching Algebra Gates Back Cover