Energy-aware system design : algorithms and architectures

Description

Cover Energy-Aware System Design ISBN 9789400716780 Preface Contents Contributors Chapter 1: Introduction 1.1 Energy Awareness 1.2 Energy-Aware Design 1.3 Exploiting Slack Toward Energy-Aware Design 1.3.1 Temporal Slack 1.3.2 Spatial Slack Enabled by Newer Process Technology 1.3.3 Behavior- and Architecture-Induced Temporal Slack: Runtime Distribution 1.3.4 Process, Voltage, Temperature, and Reliability Slack 1.3.5 Temporal and Spatial Thermal Slack 1.3.6 Peak Power Slack 1.3.7 Holistic Approach for More Slack and Better Ways to Exploit It 1.4 Introduction to Chapters References Chapter 2: Low-Power Circuits: A System-Level Perspective 2.1 Introduction 2.2 CMOS Power Consumption 2.2.1 Dynamic Power 2.2.2 Static Power 2.2.3 Analysis 2.3 Estimation of Power Consumption 2.3.1 Dynamic Power Accuracy of Estimation 2.3.2 Static Power Static Estimation Statistical Estimation 2.3.3 Temperature Estimation 2.4 Circuits to Reduce Dynamic Power 2.4.1 Clock Gating 2.4.2 Dual-Vdd Layout Architecture Level Conversion Selection of Vddl Effectiveness of Dual-Vdd 2.4.3 Other Methods 2.5 Circuits to Reduce Static Power 2.5.1 Power Gating Implementation Area and Wire Length Mode Transition 2.5.2 Body Biasing Body Biasing for Low Leakage Implementation 2.5.3 Other Techniques 2.6 Conclusion References Chapter 3: Energy Awareness in Processor/Multi-Processor Design 3.1 Introduction 3.2 Processor Power Model 3.3 Workload Characteristics Running on a Processor 3.3.1 Inter-Tasks Workload Characteristics and Classification 3.3.2 Intra-Task Workload Characteristics 3.3.3 Workload Profiling and Modeling 3.4 Basics of Dynamic Voltage and Frequency Scaling 3.5 Workload Characteristic-Aware DVFS 3.5.1 Runtime Distribution-Aware Workload Prediction 3.5.1.1 Solution Overview 3.5.1.2 Energy-Optimal Workload Prediction 3.5.1.3 Voltage and Frequency Setting 3.5.1.4 Experimental Results References Chapter 4: Energy Awareness in Contemporary Memory Systems 4.1 Introduction 4.2 Background 4.3 Energy-Aware Memory Scheduling 4.4 Explicitly Managing DRAM Power Consumption 4.5 Exploiting Emerging Technologies 4.6 Effective Data Placements 4.7 New Memory Module or Component Architectures References Chapter 5: Energy-Aware On-Chip Networks 5.1 Introduction 5.2 Conventional On-Chip Network Router Organization 5.2.1 Buffers 5.2.2 Switch 5.2.3 Arbitration 5.2.4 Latency in On-Chip Networks 5.3 Approaching Ideal On-Chip Network 5.4 Flattened Butterfly Topology 5.4.1 Concentration 5.4.2 Topology Description 5.4.3 Routing and Deadlock 5.5 Express Virtual Channel 5.5.1 Router Microarchitecture 5.5.2 Flow Control 5.6 Low-Cost Router Microarchitecture 5.6.1 Switch Organization 5.6.2 Buffer Organization 5.6.3 Arbitration 5.6.4 Routing/Flow Control Examples 5.6.5 Fairness/Starvation 5.7 Bufferless Flow Control 5.7.1 BLESS 5.7.2 SCARAB 5.8 Conclusion References Chapter 6: Energy Awareness in Video Codec Design 6.1 Introduction 6.2 Overview of H.264/AVC 6.3 H.264/AVC Video Codec 6.3.1 H.264/AVC Video Codec Architecture 6.3.2 Computational Complexity of H.264/AVC Codec 6.4 Design of Low Power H.264/AVC Codec 6.4.1 Bit Truncated Integer Motion Estimation 6.4.2 Single-Pass Fractional Motion Estimation 6.4.3 Embedded Compression 6.5 Power Scalability of H.264/AVC Codec 6.5.1 GOP Structure of Video Codec 6.5.2 Power Scalability in I-Frame Coding 6.5.3 Power Scalability in P-frame Coding 6.6 Power-Rate-Distortion Modeling of H.264/AVC Codec 6.6.1 Rate-Distortion Model 6.6.2 Power Modeling of Video Codec 6.6.3 Power-Distortion Model 6.6.4 Encoder Configuration for P-D Relationship 6.6.5 Power-Rate-Distortion Model References Chapter 7: Energy Generation and Conversion for Portable Electronic Systems 7.1 Energy Storage Devices as Power Sources 7.1.1 Battery Technologies (1) Lead-Acid Battery (2) Li-Ion Battery (3) NiMH Battery (4) Metal-Air Batteries 7.1.2 Emerging Technologies (1) Supercapacitors (2) Portable Room-Temperature Fuel Cells (3) Other Emerging Storage Technologies 7.1.3 Characterization of Batteries 7.1.3.1 Rate Capacity Effect 7.1.3.2 Recovery Effect 7.1.4 Power Source Modeling 7.1.4.1 Battery Models (1) Electrochemical Models (2) Equivalent Circuit Models (3) Analytical Models (4) Stochastic Models 7.1.4.2 Fuel Cell Power Models (1) Static Characteristics (2) Dynamic Characteristics 7.2 DC-DC Conversion and Efficiency 7.2.1 Regulator Basics 7.2.2 Linear Regulators 7.2.3 Switching Regulators 7.2.3.1 Power Dissipation of Switching Regulator (1) Conduction Power Dissipation (2) Gate Drive Power Dissipation (3) Controller Power Dissipation 7.3 Applications 7.3.1 Passive Voltage Scaling 7.3.1.1 Power Conversion Efficiency for Ultra Low-Power Microprocessors 7.3.1.2 PVS: Passive Voltage Scaling Principle of Operation Throughput Characteristics Energy Gain of PVS 7.3.1.3 Example 7.3.2 Dynamic Regulator Scheduling 7.3.2.1 Efficiencies of Voltage Regulators 7.3.2.2 Dynamic Regulator Scheduling (DRS) Problem 7.3.2.3 Example 7.3.3 Battery and Supercapacitor Hybrid 7.3.3.1 Parallel Connection 7.3.3.2 Constant-Current Charger-Based Architecture 7.3.3.3 Constant-Current Charger-Based Architecture Design Considerations 7.3.3.4 Design Example References Chapter 8: 3-D ICs for Low Power/Energy 8.1 Introduction 8.2 Thermal Characteristics of 3-D Multi-core Systems 8.2.1 Heterogeneous Thermal Coupling 8.2.2 Heterogeneous Cooling Efficiency 8.3 Temperature-Aware Power Management Techniques for 3-D Multi-core Systems 8.3.1 Definition of Power Management Problem 8.3.2 Runtime Temperature-Aware Thread Migration Techniques 8.3.2.1 IPC-Aware Thread Migration Without Considering the Thermal Characteristics in 3-D Multi-core Systems (I-Migr2D) 8.3.2.2 IPC-Aware Thread Migration Considering the Thermal Characteristics in 3-D Multi-core Systems (I-Migr3D) 8.3.2.3 IPC- and SU-Aware Thread Migration Considering the Thermal Characteristics in 3-D Multi-core Systems (IS-Migr3D) 8.3.3 Runtime Temperature-Aware Frequency/Voltage Scaling Techniques with Peak Power Constraint 8.3.3.1 DVFS with Steady-State Temperature Analysis (S-DVFS) 8.3.3.2 DVFS with Instantaneous Temperature Analysis (I-DVFS) 8.3.4 Experimental Results 8.4 Temperature-Induced Energy Minimization Techniques 8.4.1 Definition of Energy Minimization Problem 8.4.2 Runtime Power Management Techniques to Minimize Total Energy Consumption 8.4.2.1 Temperature-Aware DVFS only (T-DVFS) 8.4.2.2 Temperature-Aware Power Gating at Critical Speed (T-PG) 8.4.2.3 Temperature-Aware Integrated DVFS and Power Gating (T-INT) 8.4.2.4 Runtime Distribution-Aware DVFS only (R-DVFS) 8.4.2.5 Temperature and Runtime Distribution-Aware Integrated DVFS and Power Gating (TR-INT) 8.4.3 Experimental Results 8.5 Conclusion References Chapter 9: Low Power Mobile Storage: SSD Case Study 9.1 Power Consumption in Solid State Disk 9.2 Related Work 9.3 Flash Memory Operation and SSD Architecture 9.4 SSD Power Estimation 9.4.1 Performance and Power Modeling 9.4.2 Event-Driven Simulation 9.5 Time-Out-Based SSD Dynamic Power Management 9.6 Experiments 9.7 Summary References Chapter 10: Energy-Aware Surveillance Camera 10.1 Overview 10.2 Target System Architecture 10.2.1 Event Model 10.2.2 Operation States 10.3 Energy-Rate-Distortion Relationship of Target System 10.3.1 Event Detection 10.3.1.1 Thresholding-Based Event Detection 10.3.1.2 Edge-Based Moving Object Detection 10.3.1.3 Pattern Recognition-Based Object Detection 10.3.2 Video Encoding 10.3.2.1 Power-Rate-Distortion Model of Video Encoding 10.3.2.2 Sampling Rate 10.3.2.3 Energy Model of Video Encoding 10.3.3 Storage and Transmission 10.3.4 Problem Definition 10.4 Lifetime Maximization of Wireless Surveillance Camera 10.4.1 Definition 10.4.2 Hierarchical Event Detection 10.4.3 Storage Location Decision 10.4.4 Bit Rate Decision 10.4.5 Sampling Rate Decision 10.5 Experimental Results 10.5.1 Configuration 10.5.2 Bit Rate and Sampling Rate Control 10.6 Conclusion References Chapter 11: Low Power Design Challenge in Biomedical Implantable Electronics 11.1 Cochlear Implant 11.1.1 Background of Cochlear Implant 11.1.2 Cochlear Implant System Design 11.1.2.1 Communication 11.1.2.2 Speech Signal Processing 11.1.3 Circuit Design for Cochlear Implant 11.1.3.1 The Receiver/Stimulator Chip 11.1.3.2 Forward Data Decoder 11.1.3.3 Current Stimulator 11.1.3.4 Multichannel Current Stimulator 11.1.3.5 Backward Telemetry 11.1.3.6 Fabricated Cochlear Implant Chip 11.2 Retinal Implant 11.2.1 Background of Retinal Implant 11.2.1.1 Retinal Degeneration and Artificial Retina 11.2.1.2 Three Methods of Retinal Implants 11.2.2 Retinal Implant System Design 11.2.2.1 Electrical Stimulation Pulse 11.2.2.2 Components of Retinal Implant System 11.2.2.3 Communication 11.2.3 Circuit Design for Retinal Implant 11.2.3.1 Retinal Stimulator 11.2.3.2 Operating Modes 11.2.3.3 Battery Charging 11.2.3.4 Stimulator Array with Distributed Sensor Network 11.3 Conclusion References