System Level Design from HW/SW to Memory for Embedded Systems

Description

This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015. The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications. Front Matter ....Pages I-XII Front Matter ....Pages 1-1 Ontological User Modeling for Ambient Assisted Living Service Personalization (Maurício Fontana de Vargas, Carlos Eduardo Pereira)....Pages 3-14 Multi-Agent Based Implementation of an Embedded Image Processing System in FPGA for Precision Agriculture Using UAVs (Érico Nunes, Lucas Behnck, Carlos Eduardo Pereira)....Pages 15-26 Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study (Alexander Jungmann, Jan Jatzkowski, Bernd Kleinjohann)....Pages 27-37 Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments (Luis Feliphe Silva Costa, Alisson V. Brito, Tiago P. Nascimento, Thiago Henrique Menezes Bezerra)....Pages 38-47 Front Matter ....Pages 49-49 Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving (Lydia Jaß, Paula Herber)....Pages 51-63 Timed Path Conditions in MATLAB/Simulink (Marcus Mikulcak, Paula Herber, Thomas Göthel, Sabine Glesner)....Pages 64-76 Structural Contracts – Motivating Contracts to Ensure Extra-Functional Semantics (Gregor Nitsche, Ralph Görgen, Kim Grüttner, Wolfgang Nebel)....Pages 77-87 Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique (Tayfun Gezgin, Björn Koopmann, Achim Rettberg)....Pages 88-99 Front Matter ....Pages 101-101 Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems (Jan Jatzkowski, Marcio Kreutz, Achim Rettberg)....Pages 103-115 Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs (Andrés Goens, Jeronimo Castrillon)....Pages 116-127 Modeling and Analysis of SLDL-Captured NoC Abstractions (Ran Hao, Nasibeh Teimouri, Kasra Moazzemi, Gunar Schirner)....Pages 128-141 Front Matter ....Pages 143-143 Taming the Memory Demand Complexity of Adaptive Vision Algorithms (Majid Sabbagh, Hamed Tabkhi, Gunar Schirner)....Pages 145-158 HMC and DDR Performance Trade-offs (Paulo C. Santos, Marco A. Z. Alves, Luigi Carro)....Pages 159-171 Managing Cache Memory Resources in Adaptive Many-Core Systems (Gustavo Girão, Flávio Rech Wagner)....Pages 172-182 Front Matter ....Pages 183-183 A UML Profile to Couple the Production Code Generator TargetLink with UML Design Tools (Malte Falk, Stefan Walter, Achim Rettberg)....Pages 185-196 Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables (Kasra Moazzemi, Smit Patel, Shen Feng, Gunar Schirner)....Pages 197-209 Low Latency FPGA Implementation of Izhikevich-Neuron Model (Vitor Bandeira, Vivianne L. Costa, Guilherme Bontorin, Ricardo A. L. Reis)....Pages 210-217 Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays (Éricles Sousa, Frank Hannig, Jürgen Teich)....Pages 218-229 Back Matter ....Pages 231-231