Analysis and Design of CMOS Clocking Circuits for Low Phase Noise

Description

As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends. The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix. Cover Contents About the authors Preface Acknowledgments 1 Introduction 2 Introduction to phase noise and jitter 2.1 Definition of jitter 2.2 Power spectral density 2.2.1 Pure sine wave 2.2.2 Sine wave with narrowband phase modulation 2.2.3 Sine wave with both jitter and noise 2.3 Phase noise 2.4 Relation of phase noise and jitter References 3 CMOS oscillators 3.1 LC oscillator 3.2 Ring oscillator 3.3 Appendix: Translation of series R-L to parallel R-L References 4 Phase noise theory for CMOS oscillators 4.1 Linear time-invariant phase noise model 4.2 Time-varying phase noise model References 5 Introduction to PLL/DLL 5.1 Applications of PLL/DLL 5.2 Building blocks 5.2.1 Voltage-controlled oscillator 5.2.2 Phase detector 5.2.3 Charge pump and loop filter 5.2.4 Frequency divider 5.3 Fractional-N PLL 5.4 False locking and failure issues in PLL/DLL References 6 PLL loop dynamics and jitter 6.1 Transfer function of PLL building blocks 6.2 PLL loop dynamics 6.2.1 Second-order PLL 6.2.2 Tuning design parameters 6.2.3 PLL jitter 6.2.4 Reference spur and static phase error 6.2.5 Third-order PLL 6.2.6 Bang-bang PLL 6.3 Supply noise-induced jitter 6.3.1 Impact of supply noise to PLL jitter 6.3.2 Supply-induced jitter reduction techniques Appendix A: Analytic expression of the reference spur Appendix B: Why do we use PLL rather than FLL for frequency generation? References 7 DLL loop dynamics and jitter 7.1 DLL basics 7.2 DLL jitter 7.2.1 Input jitter transfer 7.2.2 Jitter transfer of VCDL jitter and PD/CP noise 7.3 Jitter generation and transfer of open-loop clock buffer 7.4 Design consideration on number of stages and tuning range of DLL References 8 Phase noise suppression techniques 1: subsampling PLL 8.1 Introduction 8.2 Subsampling PLL 8.3 Fractional-N SS-PLL References 9 Phase noise suppression techniques 2: all-digital PLL 9.1 Introduction 9.2 ADPLL building blocks 9.2.1 Digital loop filter 9.2.2 Time-to-digital converter 9.2.3 Digitally controlled oscillator 9.3 Quantization noise and jitter 9.3.1 Linearized model of ADPLL 9.3.2 Quantization noise of TDC 9.3.3 Quantization noise of DCO References 10 Phase noise suppression techniques 3: injection locking 10.1 Injection locking basics 10.2 Jitter transfer of ILO 10.3 Subharmonic ILO 10.4 ILO circuit implementation 10.5 Injection-locked PLL References 11 Phase noise suppression techniques 4: clock multiplying DLL 11.1 DLL with an edge-combining logic 11.2 Multiplying DLL 11.3 Offset compensation techniques 11.4 Fractional-N MDLL and ILO References Appendix A: Figure of merits (FoMs) for evaluating VCOs and PLLs Reference Appendix B: Survey on state-of-the-art clock generators References Appendix C: System Verilog modeling of CMOS clock generator including jitter Reference Appendix D: Noise sources in MOSFET transistor References Index Back Cover