Springer Handbook of Semiconductor Devices

Description

This Springer Handbook comprehensively covers the topic of semiconductor devices, embracing all aspects from theoretical background to fabrication, modeling, and applications. Nearly 100 leading scientists from industry and academia were selected to write the handbook's chapters, which were conceived for professionals and practitioners, material scientists, physicists and electrical engineers working at universities, industrial R&D, and manufacturers. Starting from the description of the relevant technological aspects and fabrication steps, the handbook proceeds with a section fully devoted to the main conventional semiconductor devices like, e.g., bipolar transistors and MOS capacitors and transistors, used in the production of the standard integrated circuits, and the corresponding physical models. In the subsequent chapters, the scaling issues of the semiconductor-device technology are addressed, followed by the description of novel concept-based semiconductor devices. The last section illustrates the numerical simulation methods ranging from the fabrication processes to the device performances. Each chapter is self-contained, and refers to related topics treated in other chapters when necessary, so that the reader interested in a specific subject can easily identify a personal reading path through the vast contents of the handbook. Foreword by Chihiro Hamaguchi Foreword by Herman Maes Preface Contents About the Editors Contributors Part I Technological Aspects 1 CMOS Manufacturing Processes 1.1 Introduction 1.2 CMOS FinFET Process 1.3 Ion Implantation 1.3.1 Beam Line Ion Implant 1.3.2 Ion Stopping 1.3.3 Amorphization and Channeling 1.3.4 Impact of Implant Process Knobs upon Resultant Distributions of Implanted Ions and Implant Damage 1.3.5 Consideration for Implant into Nonplanar Surfaces 1.3.6 Plasma Implant 1.3.7 Implant Sputtering and Backscattering 1.3.8 Implant Ion Beam Mixing 1.4 Thermal Annealing 1.4.1 Annealing Methods Rapid Thermal Annealing Laser Heating 1.4.2 Diffusion Grain Boundary and Interfacial Diffusion 1.4.3 Dopant Activation/Clustering/Deactivation 1.4.4 Semiconductor Recrystallization 1.4.5 Simulators 1.4.6 Oxidation 1.4.7 Solid Source Diffusion 1.5 Deposition 1.5.1 Deposition Methods Atomic Layer Deposition 1.6 Etch 1.6.1 Wet Etch 1.6.2 Dry Etch 1.6.3 Chemical Mechanical Polish or Chemical Mechanical Planarization 1.6.4 Etch Selectivity 1.6.5 Atomic Layer Etch 1.6.6 The Coloring Problem 1.7 Lithography 1.7.1 Fundamental Lithographic Process 1.7.2 Lithographic Constraints Due to Light Source 1.7.3 The Role of the Stepper/Scanner and Impact to Feature Resolution 1.7.4 The Role of Resist in Lithographic Process 1.7.5 Lithographic Enhancement Techniques Phase Shift Mask Optical Proximity Correction (OPC) and Inverse Lithography Antireflective Coatings 1.7.6 Multiple Patterning Approaches Pitch Division Methods Litho-Etch-Litho-Etch (LELE) Pitch Division Litho-Freeze-Litho-Etch (LFLE) Pitch Division Triple Patterning and beyond Spacer-Based Pitch Division Implant-Based Pitch Division 1.7.7 Post-optical Lithographic Techniques Extreme Ultraviolet Lithography (EUV) Nanoimprint Lithography Direct Self-Assembly as Alternative Lithography Electron Beam Lithography 1.8 Metalization and Contact Formation 1.8.1 Silicide Contact to Transistor 1.8.2 Interconnect Stack 1.8.3 Damascene Metal Processes 1.8.4 CMOS Process Technology Development through Nontraditional Techniques 1.8.5 Substrate Engineering and Hybrid CMOS Integration Epitaxially Templated Regrowth Technique Wafer Bonding Technique Semiconductor-on-Insulator Formation Transistor Architecture Advances Gate-All-Around Transistor Structure Formation Vertical Integration of Multi-Strata CMOS 1.8.6 Stress Engineering 1.9 Summary References 2 Semiconductor Memory Technologies 2.1 Introduction 2.2 Semiconductor Memories Taxonomy 2.3 Volatile Memory 2.4 SRAM Cell and Basic Operating Principles 2.5 SRAM Scaling 2.6 DRAM Cell, Array, and Basic Operating Principles 2.7 DRAM Technology Evolution 2.8 DRAM Capacitor Scaling 2.9 DRAM Access Transistor Scaling 2.10 DRAM Product Evolution 2.11 Nonvolatile Memory: The Flash Memories 2.12 Floating Gate MOSFET Devices 2.13 Flash Memory MOSFET Devices 2.14 Charge Storage Solutions 2.15 Charge Injection/Extraction Mechanisms: Programming/Erase Operations 2.16 NOR Flash Array, Operations, and Reliability Aspects 2.16.1 NOR Flash Applications and Roadmap 2.17 NAND Flash Array, Operations, and Reliability Aspects 2.18 NAND Flash Roadmap 2.19 Emerging Memories: An Insight on Phase-Change Memories 2.20 In-Memory Computing and Neuromorphic Applications References 3 BCD Process Technologies 3.1 Introduction 3.2 BCD Technology Platform Differentiation from Isolation Scheme 3.3 BCD Technology Architecture 3.3.1 Buried Layers and Epitaxial Growth 3.3.2 Deep Trench Isolation 3.3.3 Key Technology Features and Module Description 3.3.4 Latest ST Technology Platforms 3.4 New Technology Enablers for Application Evolution 3.4.1 Increase Digital Processing Capability: Lithography, Logic, and Memories 3.4.2 Power and HV Evolution: Device Architecture 3.4.3 High Current and Energy Capability 3.4.4 Passive Technology Modules for High Precision, Analog, and High Voltage Applications 3.5 Next BCD Development Challenges 3.6 Conclusions References 4 Measuring Techniques for the Semiconductor's Parameters 4.1 Transmission Electron Microscopy 4.1.1 Conventional Transmission Electron Microscopy 4.1.2 Scanning Transmission Electron Microscopy STEM Nanoanalysis 4.2 X-Ray Analytical Techniques 4.2.1 X-Ray Characteristics and Common Experimental Apparatus 4.2.2 Thin Film Analysis GeSbTe Alloys Silicides 4.2.3 Case Studies Shape-Related Structure of Silicon Nanoparticles Residual Defects in Ion-Implanted Ge Extended Defects in SiC and GaN Epilayers 4.3 Raman Spectroscopy 4.3.1 General Aspects 4.3.2 Experimental Setup 4.3.3 Structure Analysis 4.3.4 Carrier Concentration and Mobility Measurements 4.4 Electrical Parameter Measurements 4.4.1 Four-Point Probe 4.4.2 Transmission Line Model 4.4.3 Carrier Concentration Profile 4.4.4 Mobility 4.4.5 Carrier Lifetime 4.5 One-Dimensional and Two-Dimensional Electrically Active Dopant Profiling 4.5.1 Experimental Methods 4.5.2 Applications of the Methods and Examples 4.6 Optical Characterization of Semiconductors 4.6.1 Basic Concepts 4.6.2 Determination of the Optical Gap 4.6.3 Dispersion Relations 4.6.4 Impurities and Defects Absorption References 5 Interconnect Processing: Integration, Dielectrics, Metals 5.1 BEOL Integration and Performance 5.1.1 Copper Interconnect Single Damascene Scheme 5.1.2 Additional Material Films Used in the Damascene Process Flow 5.1.3 Via-First Dual Damascene Integration Scheme 5.1.4 Trench-First Dual Damascene Integration Process Flow 5.1.5 Single Patterning Versus Double Patterning 5.1.6 Trench-First Pitch-Split Double Line Patterning with Self-Aligned Via Integration Scheme 5.1.7 Self-Aligned Double Patterning (SADP) 5.1.8 2D Versus 1D Self-Aligned Double Patterning (SADP) 5.1.9 Future Outlook: EUV Single and Double Patterning 5.1.10 BEOL Performance 5.2 BEOL Dielectric Films 5.2.1 Fabrication of BEOL Low-k Dielectric Films 5.2.2 Low-k and Ultralow-k Porous pSiCOH ILD Dielectrics Dense SiCOH and Porous pSiCOH ILDs Development of Advanced pSiCOH with Improved Properties BEOL Integration Challenges for Low-k and ULK SiCOH 5.2.3 Advanced Dielectrics and Processes for Metal Interconnect Flowable Gap Fill SiCOH Pinch-Off Deposition Air Gap Novel Low-k C-Rich SiCN Dielectrics 5.2.4 Summary 5.3 BEOL Thin-Film Metals 5.3.1 Requirements for Barrier, Liner, and Seed Layers 5.3.2 Sputter Deposition Tooling for Barrier, Liner, and Seed Layers 5.3.3 Barrier/Liner/Seed Process Sequences and Enhancements Copper-Alloy Seed Layers Wetting Layers for Copper Liner Applications Copper Reflow for Damascene Feature Fill 5.4 Dielectric Cap Deposition and Interconnect Capacitance 5.4.1 SiN and SiCNH Caps Key Requirements for Dielectric Caps Effects of Reduction of SiCNH Thickness of Oxidation Barrier Properties 5.4.2 Advanced Caps with Reduced k and/or Reduced Thickness Bilayer Low-k Dielectric Cap (SiCNxH/SiCNyH) Trilayer Low-k Ultrathin Dielectric Cap (SiNx/SiNy/SiCNyH) Conformal Cyclic SiN Selective Cobalt/Dielectric Cap 5.4.3 Integration of Advanced Selective Cobalt/Dielectric Cap 5.5 Summary References 6 Wet Chemical Processes for BEOL Technology 6.1 Wet Cleaning/Etching for Cu Interconnects 6.1.1 Wet Clean Tooling 6.1.2 Wet Clean or Wet Etch Applications 6.2 Cu Electroplating 6.2.1 Background 6.2.2 Cu Plating Chemistries 6.2.3 Tooling for Copper Electroplating 6.2.4 Copper Electroplating, BEOL Yield, and Reliability 6.2.5 Extendibility of Copper Electroplating: Future Perspectives 6.3 Chemical Mechanical Planarization 6.3.1 CMP Tool Description CMP Tool CMP Pad 6.3.2 CMP Process Description 6.3.3 Copper CMP Step 1: Copper CMP – Removal of Copper Overburden Step 2: Barrier CMP – Removal of Barrier and Setting Copper Line Height 6.3.4 Control of CMP Defects 6.3.5 Copper CMP for Alternative Barrier/Seed Systems 6.3.6 Summary References 7 From FinFET to Nanosheets and Beyond 7.1 Introduction 7.2 From Pure Dimensional Scaling to Design-Technology Co-optimization 7.3 Gate-All-Around Devices: The Evolutionary Path from FinFET 7.4 High-Mobility Materials 7.5 Going 3D: CFET and Sequential 3D Integration 7.5.1 Complementary FET or CFET 7.5.2 Sequential 3D Integration 7.6 Conclusions References 8 Advanced Lithography 8.1 Lithography Basics 8.1.1 Image Formation in Lithography 8.1.2 Resolution Enhancement Techniques 8.2 Advanced Lithography Based on ArF 193 nm DUV Sources 8.2.1 Resist Thickness and Plasma Etching Selectivity 8.2.2 Multiple Patterning Techniques in ArF DUV Lithography 8.2.3 Photoresists for 193 nm DUV Lithography 8.3 Non-optical Lithographic Methods 8.3.1 Electron Beam Lithography 8.3.2 Nanoimprint Lithography 8.4 Extreme Ultraviolet Lithography 8.4.1 Requirements for EUVL Photoresists 8.4.2 Laser-Assisted Plasma Sources for EUVL 8.4.3 EUVL Chemically Amplified Photoresist Chemistry 8.5 Conclusion References 9 Advanced Technologies for Future Materials and Devices 9.1 Introduction 9.2 Nanoscale CMOS 9.2.1 FDSOI 9.2.2 Quantum Effects 9.2.3 Variability 9.2.4 Strained Channels 9.2.5 Ultimate Device Architectures 9.3 Nanoscale TFET, FE-FET, and Hybrid Devices 9.3.1 Tunnel FETs 9.3.2 Ferroelectric Gate Devices 9.3.3 Hybrid Devices 9.4 Conclusion References Part II Basic Devices and Applications 10 MOS Capacitors, MOS Transistors, and Charge-Transfer Devices 10.1 Metal-Insulator-Semiconductor Capacitor 10.1.1 Surface Potential: p-Type Substrate 10.1.2 Relation Between Surface Potential and Gate Voltage 10.2 Capacitance of the MOS Structure: p-Type Substrate 10.3 Simplified Expression of the Inversion Charge 10.3.1 Flat-Band Voltage 10.3.2 Quantitative Relations in the MOS Capacitor 10.4 MOS Photocapacitor 10.5 MOS Capacitor: n-Type Substrate 10.6 Insulated-Gate Field-Effect Transistor: MOSFET 10.7 n-Channel MOSFET: Current-Voltage Characteristics 10.7.1 Gradual-Channel Approximation 10.7.2 Differential Conductances and Drain Current, n-Channel Linear-Parabolic Model, n-Channel 10.7.3 MOSFET Theory Including the Subthreshold Current General Form of the MOSFET Current 10.8 p-Channel MOSFET: Current-Voltage Characteristics 10.8.1 Differential Conductances and Drain Current, p-Channel Linear-Parabolic Model, p-Channel 10.9 Saturation of the Drift Velocity 10.9.1 Effective Mobility and Drain-Induced Barrier Lowering 10.10 Charge-Transfer Devices 10.10.1 Charge-Coupled Devices 10.10.2 Transfer Efficiency 10.10.3 Charge-Injection Devices 10.10.4 Floating-Gate Operation 10.11 Applications of CCDs 10.11.1 Applications to Analog Filtering 10.11.2 Applications to Optical Sensing 10.12 Performances of Image Sensors 10.12.1 Spatial Resolution 10.12.2 Miscellany Dynamics and Linearity 10.13 Appendix 10.13.1 The Poisson Equation in the MOSFET Channel 10.13.2 Inversion-Layer Charge and Mobility Degradation 10.13.3 Exact Charge Partitioning in the MOS Capacitor 10.13.4 Scaling Rules for MOSFETs References 11 Electrostatic Doping and Devices 11.1 Introduction 11.2 The Concept of Electrostatic Doping 11.2.1 Schottky Barrier-Based Devices Schottky Barrier (SB) MOSFETs Reconfigurable SB-MOSFETs SB Electro-optical Devices 11.2.2 Workfunction-Induced Doping 1-D Schottky-Based Devices Gated Schottky-Based Ultrathin-Body Devices Charge Plasma Devices 11.2.3 Bias-Induced Doping Lateral p-n Junction Vertical p-n Junction: Electron-Hole Bilayer (EHB) 11.3 Electrostatic Doping Approaches: Discussion 11.3.1 Potential ED Devices for Future CMOS 11.3.2 ED: Limitations and Drawbacks 11.4 Conclusion References 12 Planar MOSFETs and Their Application to IC Design 12.1 Introduction 12.2 Planar MOSFET Evolution 12.2.1 From Bulk MOSFETs to UTBB FDSOI 12.2.2 Analog and Digital Design Needs 12.3 Model for Drain Current and First-Order Parameter Extraction 12.3.1 UTBB FDSOI Device Cross Section 12.3.2 Drain Current Model Reference to the Pao and Sah Approach Saturation Drain Voltage Ron-L Model 12.3.3 Parameter Extraction from Measurements The Threshold Voltage Extraction The Apparent Channel Mobility Degradation and the Access Resistance The Pinch-OFF and the Velocity Saturation 12.3.4 Do We Need a Quantum Approach for Ultimate Silicon-Based UTBB FDSOI? 12.3.5 Back Biased UTBB FDSOI MOSFET 12.4 MOSFETs in Analog Design 12.4.1 Inversion Level Metric 12.4.2 MOSFET gm/ID Invariance Physical Insight Short Channels Linear Versus Saturation 12.4.3 MOSFET Efficiency at High Frequency High-Frequency Distributed Effects Transadmittance Efficiency (Ym/ID) 12.4.4 Small-Signal Equivalent Circuit 12.4.5 High-Frequency Modeling Gate Resistance NQS Modeling Using Channel Segmentation 12.5 Application Example: LNA Analog Design in MI Regime 12.5.1 LNA Circuit Characteristics 12.5.2 Passives-Related Constraints and Length Selection 12.5.3 IC Selection 12.5.4 Width and VGS Calculations 12.6 Conclusions References 13 Silicon Power Devices 13.1 Introduction 13.2 Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) 13.2.1 Power MOSFETs 13.2.2 The VDMOSFET Structure Blocking Characteristics Threshold Voltage On-Resistance Switching Characteristics P-Channel (P-ch) MOSFETs and Their Value for Power Electronics Applications 13.2.3 UMOSFET Structure State-of-the-Art UMOSFETs 13.2.4 Superjunction MOSFET 13.2.5 MOSFET Body Diode 13.2.6 Edge Terminations for Silicon Power Devices 13.2.7 Epitaxial Layers and Substrate Wafers 13.3 Insulated Gate Bipolar Transistors (IGBTs) 13.3.1 Background of IGBT Development 13.3.2 IGBT Structure and Operation Switching Characteristics 13.3.3 IGBT Safe Operating Area Reverse-Biased SOA Short-Circuit SOA 13.3.4 Evolution of the IGBT Structure and Design Concept 13.3.5 IGBT Module Technologies 13.3.6 P-ch IGBT Devices 13.3.7 State-of-the-Art IGBTs Design Concepts for the IGBT Transistor Cell and Vertical Structure Reverse Blocking IGBT and Reverse Conducting IGBT Increase of the Maximum Junction Temperature and Power Density 13.3.8 Future Prospects of IGBT Devices Next-Generation Transistor Cell and Vertical Structures Intelligent Gate Drive Control Advanced Thermal Management 13.4 MOS Gate Thyristors 13.4.1 The MOS-Controlled Thyristor (MCT) 13.4.2 The Base Resistance-Controlled Thyristor (BRT) 13.4.3 The Emitter-Switched Thyristor (EST) 13.4.4 MOS Gate Thyristors and IGBT Competition 13.5 Power Rectifiers 13.5.1 Unipolar Devices 13.5.2 Bipolar Devices SSD and MPS Diodes State-of-the-Art Diode Structure References 14 Silicon Carbide Power Devices 14.1 Introduction 14.2 Ideal Specific on-Resistance for Silicon Carbide 14.3 Silicon Carbide Power Rectifiers 14.4 Silicon Power MOSFETs 14.5 SiC Power DI-MOSFET Structure 14.5.1 Blocking Characteristics 14.5.2 On-Resistance 14.5.3 Threshold Voltage 14.5.4 Reliability 14.6 Shielded SiC Planar Power MOSFET Structure 14.6.1 Device Structures 14.6.2 Gate Oxide Screening 14.6.3 Threshold Voltage 14.6.4 Channel Mobility 14.6.5 On-Resistance 14.6.6 Experimental Results 14.7 Silicon Carbide Power MOSFETs with Improved High-Frequency Performance 14.8 SiC Power MOSFET Body-Diode 14.9 Silicon Carbide Power JBSFETs 14.10 Unclamped Inductive Switching Stress 14.11 Short-Circuit Capability 14.12 Shielded Trench-Gate Power MOSFET Structure 14.12.1 Device Structure 14.12.2 On-Resistance 14.12.3 Experimental Results 14.13 SiC Trench-Gate MOSFET with Thick Trench Bottom Oxide 14.14 SiC Trench-Gate MOSFET with Deep P+ Trench Regions 14.15 SiC V-Groove Trench-Gate MOSFET 14.16 Silicon Carbide Bi-Directional Field Effect Transistor 14.17 Commercial Devices 14.18 Silicon Carbide Power Device Applications 14.19 Conclusions References 15 GaN-Based Lateral and Vertical Devices 15.1 GaN Material and Epitaxy 15.1.1 Typical Layer Stacks for Lateral GaN Power Transistors 15.1.2 Substrates, Nucleation, and Strain Management 15.1.3 Growth on SiC Substrates 15.1.4 Growth on Si Substrates 15.1.5 Back-Barrier Selection 15.1.6 HEMT Heterostructures 15.2 Lateral Devices Architectures 15.2.1 Applications 15.2.2 State-of-the-Art 15.2.3 Limitations of GaN Lateral Devices Parasitic Conduction Under High Voltage Dynamic RON Issues 15.2.4 Pushing the Limits of Lateral GaN Devices: Enhancement of the Blocking Voltage 15.2.5 Normally-Off GaN Lateral Devices MISHEMTs F− Ion Implant under the Gate The Cascode Circuit P-GaN Processing of GaN Lateral Devices Future Prospects 15.3 Vertical Devices Architectures 15.3.1 Device/Circuit Hybrid Modeling 15.3.2 Physics Models for GaN Drift-Diffusion Model B. Polarization Electron Mobility Device Modeling Calibration Modeling of Vertical GaN Devices 15.3.3 A Review of CAVET 15.3.4 Operation Principle of the CAVET 15.3.5 Trench CAVET 15.3.6 Vertical MOSFETs 15.3.7 Regrowth-Based Vertical MOSFET (OGFET) 15.3.8 Static Induction Transistor 15.3.9 Conclusions on GaN Vertical Transistors 15.4 Parasitics and Reliability 15.4.1 Charge-Trapping in GaN-Based Power HEMTs 15.4.2 Methods to Investigate Charge- Trapping Phenomena 15.4.3 Performance and Characteristics of GaN Devices and Challenges 15.4.4 Reliability Issues of GaN-Based Power HEMTs 15.4.5 Gate-Stack Reliability 15.4.6 Off-State Reliability 15.4.7 Stability in Semi-on Conditions 15.5 Conclusions References 16 Bipolar Transistors and Silicon Diodes 16.1 The PN Junction 16.1.1 Introduction 16.1.2 The PN Junction at Equilibrium and in Reverse Bias Potentials and Charges: Electrostatics Analysis at Equilibrium Analysis of the pn Junction in Reverse Bias 16.1.3 The pn Junction in Forward Bias Estimation of the Minority Carrier Concentrations The Current-Continuity Equation Minority-Carrier Current Simplifying Assumptions Total Current Densities Additional Generation and Recombination Currents from the Space-Charge Region 16.2 Bipolar Transistors 16.2.1 Introduction 16.2.2 Structure 16.2.3 Principle of Operation 16.2.4 DC Operation of the n-p-n BJT Under Forward Active Mode 16.2.5 Bipolar-Transistor Configurations 16.2.6 Common-Emitter Configuration 16.2.7 Common-Collector Configuration 16.2.8 Common-Emitter Amplifier 16.3 The Metal-Semiconductor Schottky Diode 16.3.1 Introduction Energy Analysis of Isolated Metal-Semiconductor Systems Energy Distribution Across a Metal-Semiconductor Contact The Schottky Diode Under Non-equilibrium 16.3.2 Additional Factors References 17 Memory Challenges 17.1 Overcoming the Concept of Universal Memory 17.2 “NVM Candidates” 17.2.1 OxRAM 17.2.2 Phase Change Memory (PCM) 17.2.3 MRAM 17.2.4 FeFET 17.3 How eNVMs Compare to Each Other 17.3.1 eNVMs Comparison 17.3.2 Most Relevant eNVM Demonstrators 17.3.3 Innovative Applications 17.4 eNVM for Neuromorphic Applications 17.5 Memory Selectors References 18 Physical sensors drive MEMS consumerization wave 18.1 Overview 18.2 Present and Future Market Applications of Sensors 18.2.1 Automotive Micro-sensors 18.2.2 The Sensor Consumerization Wave Sensors for User Interface in Game Consoles Sensors for Multiple Functions in Smartphones, Tablets, and Wearables 18.2.3 The Internet of Things Era Wireless Sensor Networks 3-D Sensing Solutions 18.3 Micro-sensor Classification and Terminology 18.3.1 Classification 18.3.2 Terminology 18.4 Microfabrication and Micromachining 18.5 Microsystem Back End 18.5.1 Micro-sensor Assembly and Packaging 18.5.2 Micro-sensor Testing and Calibration 18.6 Accelerometers 18.6.1 Accelerometers Introduction 18.6.2 Accelerometer Specifications 18.6.3 Accelerometer System 18.6.4 Capacitive MEMS Accelerometers: Design Principles 18.6.5 Capacitive MEMS Accelerometers: Process Flow 18.6.6 Reliability Challenges for MEMS Accelerometers 18.6.7 Next-Generation MEMS Accelerometers 18.7 Gyroscopes 18.7.1 Gyroscopes Introduction 18.7.2 Gyroscopes Specifications 18.7.3 Gyroscope System 18.7.4 Capacitive MEMS Gyroscopes: Design Principles 18.7.5 Capacitive MEMS Gyroscopes: Process Flow 18.7.6 Reliability Challenges for MEMS Gyroscopes 18.7.7 Next-Generation MEMS Gyroscopes 18.8 Microphones 18.8.1 Microphones Introduction 18.8.2 Capacitive MEMS Microphones 18.8.3 Piezoelectric MEMS Microphones 18.8.4 Reliability Challenges for MEMS Microphones 18.9 Pressure Sensors 18.9.1 Pressure Sensors Introduction 18.9.2 VENSENS™ Pressure Sensor 18.9.3 Bastille™ Pressure Sensor 18.9.4 Reliability Challenges for MEMS Pressure Sensors 18.10 Magnetometers 18.10.1 Magnetometers Introduction 18.10.2 Hall Sensors 18.10.3 Magnetoresistive Sensors 18.10.4 Anisotropic Magnetoresistive Sensors 18.11 Silicon Image Sensors and Evolutions of CMOS 18.11.1 Introduction 18.11.2 CCD and CMOS CMOS Structure: From Photodiode to Pixel Readout SPAD and SiPM SPAD Structure SiPM 18.11.3 CMOS Image Sensor: A Complete Solution CMOS and Sensor Integration Pixel Manufacturing, FSI, BSI, and 3-D Stack 3-D Integration 3-D Sensing Stereo Light Structured Light Time of Flight Direct Time of Flight and Indirect Time of Flight Optical Parameters and Field of View References 19 Solar Cells 19.1 Background and Basic Operation of Solar Cells 19.2 Solar Spectrum and Optical Properties 19.2.1 Solar Irradiance 19.2.2 Optical Properties of Photovoltaic Materials 19.3 Theory of Operation of Conventional Solar Cells 19.3.1 Dark Current and Recombination Recombination and Minority Carrier Lifetime Dark Current 19.3.2 Photocurrent 19.3.3 Series Resistance 19.3.4 Heterojunction Cells and Carrier Selective Contacts Heterojunctions Thermodynamic and Detailed Balance Definition of Ideal Contacts Silicon-Based Selective Carrier Contact Solar Cells 19.4 Performance Comparison of Single Junction Technologies 19.4.1 Performance Limits of Si- and GaAs-Based Technologies 19.4.2 Thin Film Technology 19.4.3 Organic Solar Cells 19.5 Efficiency Limits for Photovoltaic Converter 19.5.1 Shockley-Queisser Limit 19.5.2 Overcoming the Shockley-Queisser Limit 19.6 Multijunction Solar Cells 19.7 Nanotechnology-Based Approaches 19.7.1 Nanomaterials 19.7.2 Dye-Sensitized and Quantum Dot Solar Cells 19.7.3 Light Management in Photovoltaics 19.7.4 Nanowire Solar Cells 19.8 Advanced Concept Photovoltaics 19.8.1 Intermediate Bands 19.8.2 Multiple Exciton Generation (MEG) 19.8.3 Hot Carrier Solar Cells 19.9 Summary References 20 X-Ray Detectors 20.1 Introduction and Fundamental Concepts 20.2 X-Ray Spectroscopic Detectors 20.3 Flat Panel X-Ray Image Detectors 20.4 Signal and Noise 20.4.1 Responsivity 20.4.2 Signal and Linearity 20.4.3 Noise Sources in the Detector 20.5 Image Resolution 20.6 Detective Quantum Efficiency (DQE) 20.7 Pixelated Detectors and Small Pixel Effect 20.8 Image Lag and Ghosting References 21 Photodetectors Based on Emerging Materials 21.1 Background of Graphene-Based Photodetectors 21.2 Performance Metrics of Photodetectors 21.2.1 Responsivity (Rph) 21.2.2 Quantum Efficiency 21.2.3 Noise Equivalent Power (NEP) 21.2.4 Detectivity (D*) 21.2.5 Linear Dynamic Range (LDR) 21.2.6 Response Speed 21.2.7 Photoconductive Gain (Gph) 21.3 Physical Mechanisms for Photodetection 21.3.1 Photovoltaic Effect 21.3.2 Photothermoelectric Effect 21.3.3 Bolometric Effect 21.3.4 Plasma-Wave-Assisted Mechanism 21.3.5 Photogating Effect 21.4 Practical Realization of Graphene Photodetectors 21.4.1 Metal-Graphene-Metal (MGM) Photodetectors (PV and PTE Effects) 21.4.2 Graphene-Based Bolometers 21.4.3 Plasmonics-Enhanced Graphene Photodetectors 21.4.4 Detectors Based on Photogating 21.5 Graphene-Based Heterostructures for Photodetectors 21.5.1 Graphene/Silicon 21.5.2 Graphene/III–V Semiconductors 21.5.3 Graphene/Organic Semiconductors 21.5.4 Graphene/Perovskites 21.5.5 Graphene/Other 2D Materials 21.6 Integrated Graphene Photodetectors 21.6.1 Integration with Optical Cavity 21.6.2 Integration with Waveguides 21.7 Graphene Photodetectors with Special Geometry or Architectures 21.8 Conclusions and Outlook References 22 Terahertz Electronic Devices 22.1 Introduction 22.2 Gunn Diodes 22.2.1 Transit-Time Mode Gunn Oscillations 22.2.2 Materials for Gunn Diodes 22.2.3 Realisations of Gunn Oscillators 22.2.4 Perspectives 22.3 Schottky Diodes 22.3.1 Terahertz Schottky Junction 22.3.2 Parasitics of Terahertz Schottky Planar Diode 22.3.3 Terahertz Schottky Multipliers and Mixers 22.3.4 Driving Application of THz Schottky Diodes 22.3.5 Perspectives 22.4 Resonant Tunnelling Diodes 22.4.1 Resonant Tunnelling 22.4.2 RTD Oscillators 22.4.3 Frequency Limitations of RTDs 22.4.4 Applications of RTDs 22.4.5 Perspectives 22.5 Field-Effect Transistors 22.5.1 Frequency Limitations of FETs 22.5.2 FETs as THz Detector 22.5.3 FETs as THz Emitters 22.5.4 Perspectives 22.6 Heterojunction Bipolar Transistors 22.6.1 Physics of the Heterojunction Bipolar Transistor The PN Junction The Bipolar Transistor The Heterojunction Bipolar Transistor (HBT) Complete Small-Signal Equivalent Circuit Reduction of the Total Emitter-Collector Transit Time τEC and the Base Resistance Performances and Limitations of HBTs 22.6.2 Different Technologies of Heterojunction Bipolar Transistors III-V HBTs III-V and SiGe HBTs Comparison 22.6.3 HBT-Based Circuits Compact Modelling for Circuit Design Performances of HBTs-Based Circuits 22.6.4 Perspectives 22.7 Complementary Metal Oxide Semiconductor Transistors 22.7.1 Emitters 22.7.2 Detectors 22.7.3 Perspectives 22.8 Ballistic Rectifiers 22.8.1 Ballistic Formalism 22.8.2 BR Electrical Characteristics 22.8.3 THz BR Detection 22.8.4 Perspectives 22.9 Conclusions References 23 Semiconductor Lasers 23.1 Fundamentals 23.1.1 Gain Medium 23.1.2 Pump Process 23.1.3 Resonator 23.2 Technical Properties 23.2.1 Introduction 23.2.2 Fundamental Behavior 23.2.3 Dynamics 23.2.4 Spectral Properties and Coherence 23.2.5 Beam Quality 23.2.6 Polarization 23.2.7 Optical Power 23.2.8 Temperature Dependence 23.3 Materials and Architectures 23.3.1 Semiconductor Materials 23.3.2 Quantum Confinement Structures 23.3.3 Quantum Cascade Lasers 23.3.4 Microcavity Lasers 23.4 Applications and Outlook 23.4.1 Applications 23.4.2 Outlook References Part III New-Generation Devices and Architectures 24 Heterojunction Tunnel Field-Effect Transistors 24.1 Introduction 24.2 Tunnel FET Operation Principles 24.3 Band-to-Band Tunneling 24.4 Subthreshold Swing 24.5 ON Current 24.6 OFF Current 24.7 Output Characteristics 24.8 Ambipolar Conduction 24.9 Heterojunction Tunnel FETs 24.9.1 Vertical Heterojunction TFET 24.9.2 Lateral Heterojunction TFET 24.9.3 Vertical Nanowire HTFET 24.9.4 Layered Two-Dimensional HTFET 24.9.5 III-Nitride HTFETs 24.10 Band Tails 24.11 Composite TFET/MOSFET 24.12 Complex Gate Dielectrics 24.13 Technology Benchmarks 24.14 Summary and Concluding Remarks References 25 Carbon-Based Field-Effect Transistors 25.1 General Properties of Graphene and Carbon Nanotubes 25.2 Graphene-Based Transistors 25.2.1 Band Structure of Graphene 25.2.2 Basic Device Geometry and Characterization 25.2.3 Contact Resistance 25.2.4 Radio Frequency Transistors 25.2.5 Flexible Transistors for High-Frequency Applications 25.2.6 Vertical Transistors/Hot Electron Transistors 25.2.7 Metal-Insulator-Graphene (MIG) Diodes 25.3 Carbon Nanotube-Based Transistors 25.3.1 Band Structure of CNT 25.3.2 CMOS and Integrated Digital Circuits Based on CNT 25.4 Summary References 26 Negative Capacitors and Applications 26.1 Introduction 26.1.1 Classification of Next-Generation Transistors 26.1.2 Phase Transition and Landau Theory 26.2 Device Physics of NCFETs 26.2.1 Phenomenological Theory of NCFETs 26.2.2 Tailoring Negative Capacitance by Energy Landscape Engineering 26.2.3 Reliability Physics of NCFETs 26.2.4 Advanced Issues 26.3 Device Physics of PhaseFETs 26.3.1 Behavioral Compact Model 26.3.2 Physics-Based Phenomenological Model 26.3.3 Experimental Results on PhaseFETs 26.4 Boolean Computing with NCFETs, FeFETs, and PhaseFETs 26.4.1 Logic Design 26.4.2 SRAM Design 26.4.3 Nonvolatile Memory Design 26.5 Non-boolean Computing with NCFETs, FeFETs, and PhaseFETs 26.5.1 Coupled Oscillator-Based Computing 26.5.2 Neuromorphic Computing 26.6 Summary and Conclusions References 27 Flexible Electronics and Bioelectronics Devices 27.1 Flexible Electronic Devices and Fabrication 27.1.1 Key Materials Amorphous Silicon Low-Temperature Polycrystalline Silicon Amorphous Oxide Semiconductors Organic Semiconductors 27.1.2 Fabrication Methods Vacuum Depositions Printing Techniques Ink Formulation and Printability 27.1.3 Printable and Flexible Transistors TFT Device Architectures Issues of Printed Organic TFTs Developments in Printable Organic TFTs All-Printed Organic TFTs 27.2 Modelling of Flexible TFTs and Circuit Design Considerations 27.2.1 TFT Compact Modelling Computer-Aided Design Cambridge's TFT Model Computer Interpretation of Device Model CAMCAS Model in Simulation Environment 27.2.2 Small-Signal Modelling General Small Models TFT Small-Signal Model Model Validation 27.2.3 Subthreshold Operation for Schottky Barrier TFTs Introduction Subthreshold Model for IGZO TFTs Figures of Merit Sensitivity to Variations and Bias 27.3 Applications of Flexible Electronics in Biological Sensing 27.3.1 Current Mainstream Biosensing Technologies 27.3.2 Semiconductor Technologies for Biosensing 27.3.3 Fully Integrated CMOS Biosensor 27.3.4 Heterogeneously Integrated Biosensor with Disposable Electrodes 27.3.5 Impedance-Based Immunosensor jin2019disposable 27.3.6 TFT-Based Biosensors References 28 Biodegradable Electronics 28.1 Materials 28.1.1 Terminology 28.1.2 Polymeric Substrates and Encapsulations 28.1.3 Metallic Conductors 28.1.4 Semiconductors 28.1.5 Dielectrics 28.2 Devices, Circuits, and Systems 28.2.1 Transistors and Circuits 28.2.2 Sensors 28.2.3 Optical Devices: LEDs 28.2.4 Powering Devices: Batteries, Photovoltaics,and Energy Harvesters 28.3 Dissolution Mechanisms 28.4 Fabrication Examples 28.5 Application, Grand Challenges, and Outlook References 29 Resistive-Switching Memories 29.1 Introduction 29.2 Physical Mechanism of Resistive Switching 29.2.1 Ox-RRAM 29.2.2 CBRAM 29.3 Modeling and Simulation of Resistive-Switching Behaviors 29.3.1 Ox-RRAM 29.3.2 CBRAM 29.4 Array Design and Optimization 29.4.1 Crossbar Array 29.4.2 Selector Devices for RRAM Array 29.4.3 3D Integration 29.5 Applications 29.5.1 Embedded Memory 29.5.2 Computing in Memory 29.5.3 Brain-Inspired Computing 29.6 Summary and Prospect References 30 Phase-Change Memories 30.1 Introduction 30.2 PCM Development 30.2.1 A Historical Overview 30.2.2 PCM Placement in the Non-volatile Memory Market 30.3 Basics of the PCM Technology 30.3.1 Optical and Electrical Properties of Chalcogenide Materials 30.3.2 Device Operation 30.3.3 The Ovonic Threshold Switching Thermal Models Electronic Models Structural Models 30.3.4 Memory Switching and the Physics of Phase Change 30.4 Materials and Devices 30.4.1 Materials and PCM Performances 30.4.2 PCM Device Architectures Contact-Minimized Cells Volume-Minimized Cells Cross-Point Arrays 30.5 Reliability and Perspectives 30.5.1 PCM Reliability Data Retention Cycling Endurance Read Disturb Thermal Disturb 30.5.2 Performance Improvements and Perspectives References 31 Spin-Based Devices for Digital Applications 31.1 Introduction 31.1.1 MOSFETs: Recent Developments 31.1.2 Electron Spin as a Complement to Charge 31.2 Spin-Based Switches for Digital Applications 31.2.1 Electric Spin Injection into Semiconductors Spin-Dependent Trap-Assisted Hopping from a Ferromagnet to Silicon Spin-Dependent Hopping in Magnetic Tunnel Junction 31.2.2 Single-Spin Transistor 31.2.3 Silicon SpinMOSFET and SpinFET 31.2.4 Spin Relaxation Suppression in Silicon Films 31.2.5 Perspectives of a Spin Silicon Switch 31.3 Nonvolatile Magnetoresistive Memories 31.3.1 Spin-Transfer Torque MRAM 31.3.2 Spin-Orbit Torque MRAM 31.3.3 Advanced MRAM Developments 31.3.4 Racetrack Memory 31.4 Spintronic Logic 31.4.1 Magnetic Domain Wall Logic 31.4.2 Logic-in-Memory 31.4.3 Stateful Logic 31.4.4 Buffered Magnetic Logic Environment 31.4.5 All-Spin Logic 31.4.6 Benchmarking and Magnetoelectric Spin-Orbit Logic References 32 Memristive/CMOS Devices for Neuromorphic Applications 32.1 Introduction 32.2 Memory Transistor and Mainstream Flash Technologies 32.3 Neuromorphic Networks Based on Memory Transistor Synaptic Arrays 32.4 Neuromorphic Networks Based on SRAM Arrays 32.5 Memristive Devices 32.5.1 2-Terminal Memristive Devices 32.5.2 3-Terminal Memristive Devices 32.6 Neuromorphic Networks with Memristive Devices 32.6.1 SNNs with Memristive Devices 32.6.2 DNNs with Memristive Devices 32.7 Discussion 32.8 Conclusions References 33 Nanoelectronic Systems for Quantum Computing 33.1 Introduction 33.1.1 Moore's Law 33.1.2 Where the Industry Appears to Be Going 33.1.3 New Computational Models: Quantum Computing 33.1.4 State of the Art in Quantum Computing 33.2 Qubits and Entanglement 33.2.1 Bits and Qubits 33.2.2 Qubits as Two-Level “Atoms” 33.2.3 Entanglement 33.3 The Silicon Qubit 33.4 The Josephson-Based Qubit 33.4.1 The Charge Qubit 33.4.2 The Flux Qubit 33.4.3 The Hybrid Charge-Flux Qubit 33.4.4 Coupling Qubits 33.5 Integrated Optics 33.5.1 The Jaynes-Cummings Model 33.5.2 Qubits 33.5.3 Qubits and Gates 33.6 Other Qubits 33.6.1 NV Centers 33.6.2 Braiding 33.6.3 Surface Bonds 33.6.4 Flying Qubits 33.7 Summary and Conclusions References Part IV Modeling 34 Compact/SPICE Modeling 34.1 Introduction 34.2 Passive SPICE Models 34.2.1 Resistor 34.2.2 Resistor R3_CMC 34.2.3 Thin Film Resistor 34.2.4 Capacitor 34.2.5 Moscap 34.2.6 Capacitor with Frequency-Dependent Capacitance 34.2.7 Chip Capacitor 34.2.8 CPW Capacitor 34.2.9 Inductor 34.2.10 Inductor Coupling Coefficient 34.2.11 Linear Controlled Sources 34.2.12 Dynamic Nonlinear Sources 34.2.13 Transmission Lines 34.2.14 Linear Models for Transmission Line Systems 34.3 Active SPICE Models 34.3.1 Diode JUNCAP Model 34.3.2 Photo Diode 34.3.3 Fowler-Nordheim Diode 34.3.4 BJT Ebers and Moll BJT Model Gummel-Poon (GP) BJT Model VBIC Vertical BJT Model MEXTRAM Model HiCUM IGBT 34.3.5 MOSFETs Berkeley Short-Channel IGFET Model HSPICE Level28 BSIM3 BSIM4 BSIM6 Philips MOS Model 9 Philips MOS Model 11 PSP MOSFET Model EKV2.6 EKV3 HiSIM MOSFET Model Other MOSFET Compact Models 34.3.6 SOI MOSFET Models PD SOI MOSFET BSIM SOI HiSIM SOI Leti L-UTSOI UFSOI/UFPDB/UFDG 34.3.7 JFETs 34.4 HV/Power Compact Models 34.4.1 LDMOS 34.4.2 MM20 LDMOS Model 34.4.3 HiSIM-HV: A Compact Model 34.5 Organic TFT 34.5.1 RPI a-Si TFT Model 34.5.2 AIM-SPICE MOS15 34.6 Progressive Modeling Directions 34.6.1 Single-Electron Transistors (SET) 34.6.2 Quantum Dot 34.6.3 Resonant Tunneling Diode 34.6.4 Rapid Single-Flux Quantum (RSFQ) Device 34.6.5 Memristor 34.6.6 Negative Capacitance Model 34.6.7 Magnetic Tunnel Junction 34.7 Conclusions References 35 Process Simulation 35.1 Scope and History of Process Simulation 35.2 Simulation of Ion Implantation 35.2.1 Analytical Models 35.2.2 Monte Carlo Simulation 35.3 Simulation of Diffusion and Activation 35.3.1 Intrinsic Point Defects and Impurities 35.3.2 Basic Diffusion and Reaction Mechanisms 35.3.3 Macroscopic Diffusion Behavior of Dopants 35.3.4 Dopant Diffusion at High Concentrations 35.3.5 The Influence of Surface Processes on Dopant Diffusion 35.3.6 Transient Diffusion Effects During Post-Implantation Annealing 35.3.7 Electrical Activation, Clusters, and Solid Solubility 35.3.8 Segregation 35.3.9 Simulation Methodologies 35.4 Simulation of Oxidation 35.4.1 One-Dimensional Simulation of Oxidation 35.4.2 Multidimensional Simulation of Oxidation 35.4.3 Multidimensional Simulation of Stress-Dependent Oxidation 35.5 Lithography Simulation 35.5.1 Basic Principle of Lithography 35.5.2 Principle of Lithography Simulation 35.5.3 Simulation of Imaging 35.5.4 Simulation of Resist Development 35.5.5 State-of-the-Art Lithography Simulation 35.5.6 Examples for State-of-the-Art Lithography Simulation 35.6 Simulation of Deposition and Etching 35.6.1 Outline of Equipment Simulation 35.6.2 Discretization and Movement of Surfaces 35.6.3 Models for Deposition and Etching Rates 35.7 Process Variations 35.7.1 Sources of Systematic Process Variations 35.7.2 Hierarchical Simulation of the Impact of Process Variations 35.8 Conclusions References 36 A Digital Twin for MEMS and NEMS 36.1 General Considerations 36.1.1 Digital Twinning for MEMS and NEMS 36.1.2 A Formal Classification System for MEMS and NEMS Physical Scales and Details Numerical Techniques and Computational Methodologies 36.1.3 The Structure of the Chapter 36.2 Analytical Modeling 36.2.1 Introduction 36.2.2 Analytical Mechanics of MEMS 36.2.3 Dynamics of Electromagnetic Levitation Micro-Systems 36.2.4 Stability of Electromagnetic Levitation Micro-Systems Application 36.2.5 Phenomenological Model of Heat Transfer in Hard-Disk Air Bearing Nonlocal Behavior in Air Molecule: Governing Equation in Air Bearing Discussion 36.3 Topology Optimization 36.3.1 General Considerations in Topology Optimization Variational Problem and Regularization Adjoint Analysis Numerical Implementation 36.3.2 Applications in Microfluidics and Nano-Optics Topology Optimization for Microfluidics Low Reynolds-Number: Topology Optimization of Micromixers Large Surface-to-Volume Ratio: Topology Optimization of Microtextures for Cassie-Baxter Wettability Topology Optimization for Nano-Optics Dielectric Nanostructure: Topology Optimization of Metalens Metal Nanostructure: Topology Optimization for Localized Surface Plasmon Resonances 36.4 Model Order Reduction 36.4.1 Reduced Basis Method for Steady Linear Parametric Systems Reducing the complexity of fr(μ,xr(μ)) in the ROM (36.76) 36.4.2 Structure Preserving MOR for Nonlinear Port-Hamiltonian Systems Structure Preserving MOR with DEIM 36.4.3 Application to Topology Optimization 36.5 Conclusions References 37 Macroscopic Transport Models for Classical Device Simulation 37.1 History of Classical Device Simulation 37.1.1 Structure of the Review 37.2 The Phenomenological Drift-Diffusion Model 37.2.1 Poisson's Equation and the Continuity Equation 37.2.2 Drift and Diffusion Current Drift Current Diffusion Current 37.2.3 The Semiconductor Equations 37.2.4 Parameter Modeling Mobility Carrier Generation and Recombination 37.3 Microscopic Transport Modeling 37.3.1 The Boltzmann Transport Equation 37.3.2 The Band Structure 37.3.3 Macroscopic Observables 37.3.4 Analytical Distributions Fermi-Dirac and Maxwell-Boltzmann Heated Displaced Maxwellian Diffusive Maxwellian 37.3.5 The Microscopic Relaxation Time Approximation 37.3.6 Microscopic Generation and Recombination 37.4 Macroscopic Transport Models 37.4.1 The Method of Moments 37.4.2 The Macroscopic Relaxation Time Approximation 37.4.3 The Closure Problem 37.4.4 Moment Equations for a Parabolic Band 37.4.5 Hydrodynamic Models Isotropic Symmetry Phenomenological Highest-Order Moment Closure Numerical Properties 37.5 Energy Transport Models 37.5.1 The Diffusion Approximation 37.5.2 Diffusion Scaling 37.5.3 Stratton's Approach 37.5.4 Bløtekjær's Approach Three-Moment Energy Transport Model Four-Moment Energy Transport Model Discussion of Bløtekjær's Closure 37.5.5 Relaxation Times and Carrier Mobilities Mobility Energy Relaxation Time 37.5.6 Bløtekjær Versus Stratton Approach 37.6 Limits of Validity for Drift-Diffusion and Energy Transport Models 37.6.1 Critical Issues Non-parabolic Band Structure Tensor Quantities and Anisotropy Drift Energy Versus Thermal Energy Highest-Order Moment Closure Mobilities and Relaxation Times Complexity of Models 37.6.2 Non-Maxwellian Energy Distribution Qualitative Analysis Shape of the Distribution Function 37.6.3 Numerical Evaluation Modeling of Velocity Overshoot Limitations of the Drift-Diffusion Model Drift-Diffusion Versus Energy Transport Spurious Velocity Overshoot 37.7 Advanced Macroscopic Transport Models 37.7.1 Ansatz-Based Approaches 37.7.2 Higher-Order Moment Models Properties of the Kurtosis Modeling of the Transport Parameters 37.7.3 Table-Based Parameter Modeling 37.8 Applications 37.8.1 n+nn+ Test Structures Model Check Velocity Profile Drain Current 37.8.2 A Double-Gate MOSFET Drain Current Velocity Predictiveness Numerical Properties 37.8.3 Modeling of Hot-Carrier Effects Kurtosis Velocity Overshoot Impact Ionization Hot-Carrier Gate Currents Hot-Carrier Degradation 37.9 Summary and Conclusion References 38 Grid generation and algebraic solvers 38.1 Introduction and Motivations 38.2 Modeling Semiconductor Devices 38.2.1 The Scaled Dimensionless DD Model 38.3 The Gummel Map 38.3.1 Toward the Numerical Solution of the Gummel Map 38.3.2 The Discretization of the Gummel Map 38.4 The Fully Coupled Newton Approach 38.5 Grid Generation: The Basics 38.5.1 Structured Meshes 38.5.2 Unstructured Meshes 38.5.3 Hybrid Meshes 38.5.4 Advanced Techniques: Mesh Adaptation Evaluation of the Discretization Error The Adaptive Procedure 38.5.5 Meshes for Semiconductor Devices 38.6 Algebraic Solvers 38.6.1 Nonlinear Solvers 38.6.2 Linear Solvers 38.7 The n-MOSFET Test Case 38.7.1 Comparison of Sparse Solution Techniques 38.7.2 Numerical Assessment References 39 Spherical Harmonics Expansion and Multi-Scale Modeling 39.1 Introduction 39.2 The Spherical Harmonic Expansion Method 39.2.1 The Boltzmann Transport Equation 39.2.2 Spherical Harmonics Expansion 39.2.3 Results 39.3 Multi-Scale Modeling 39.3.1 Sequential Multi-Scale Modeling 39.3.2 Concurrent Multi-Scale Modeling 39.4 Numerical Solution of the Drift-Diffusion Model: Some Historical Remarks 39.5 Conclusion References 40 Charge Transport Models for Amorphous Chalcogenides 40.1 Amorphous Semiconductors 40.2 Atomic Structure and Electronic States 40.2.1 Atomic Structure of Amorphous and Crystalline Chalcogenides 40.2.2 Electron States in Amorphous and Crystalline Chalcogenides 40.2.3 Resistance Drift 40.3 Physical Models and Numerical Approaches to Charge Transport 40.4 Microscopic Models 40.4.1 A Hydrodynamic Approach to Trap-Limited Transport 40.4.2 Inclusion of Dispersive Band States 40.4.3 Detrapping Due to Electron-Electron Interaction 40.4.4 3D Simulation on a Random Network 40.4.5 Inter-Trap Transitions 40.4.6 Ab Initio Quantum Transport Models for Ultrascaled Chalcogenide Devices 40.5 Macroscopic Models 40.5.1 Macroscopic Modeling of PCM Oscillations 40.5.2 Measuring PCM Characteristics in the Amorphous Phase 40.5.3 Thermal Analysis of the PCM 40.5.4 Comparison with Experiments 40.5.5 Stability Analysis of PCM Oscillations 40.6 Open Challenges in Modeling: A Brief Outline References 41 Application of the k p Method to Device Simulation 41.1 Introduction 41.2 The Eight-Band k ·p Model 41.2.1 Bulk Unstrained Semiconductors 41.2.2 Strained Semiconductors 41.2.3 Confined Structures 41.3 The k·p Method Applied to Tunnel Field-Effect Transistors 41.3.1 Device Structures 41.3.2 Impact of Strain on the Tunneling Current of Homojunction TFETs 41.3.3 Impact of Strain on the Tunneling Current of Heterojunction TFETs 41.3.4 GaSb-/InAs-Based TFET Optimization Exploiting Strain and Device Geometry 41.4 TFET Inverters for a Complementary Technology Platform 41.5 Modelling of Interface Traps in the k · p Scenario 41.6 Conclusions References 42 Ab initio Methods for Electronic Transport in Semiconductors and Nanostructures 42.1 Introduction 42.2 Historical Overview 42.2.1 The Deformation Potential Theorem 42.2.2 The Rigid (Pseudo)ion 42.3 Theoretical Framework 42.3.1 Density Functional Perturbation Theory 42.3.2 Finite-Displacement Method 42.3.3 Electron-Phonon Interaction 42.3.4 Ab initio Simulation of Electronic Transport: The Monte Carlo Method 42.4 Silicon, Group-III Nitrides, and 2D Materials 42.4.1 Silicon 42.4.2 Group-III Nitrides GaN AlN 42.4.3 2D Materials Phosphorene Silicene and Germanene 42.5 Dielectric Response of Low-dimensional Materials 42.5.1 Density-Density Response Function 42.5.2 Microscopic Poisson Equation 42.5.3 Microscopic Dielectric Tensor of 1D Materials Microscopic Dielectric Tensor of a 7-aGNR Ribbon-Width Dependence of the Dielectric Permittivity Microscopic Dielectric Tensor of a 3 3 Silicon Nanowire 42.5.4 Microscopic Dielectric Permittivity of 2D Materials 42.5.5 Discussion 42.6 Quantum Transport 42.6.1 Ballistic Transport 42.6.2 Numerical Approach Envelope Functions Self Energies Self-Consistency 42.6.3 Scattering—The Pauli Master Equation 42.6.4 Example 1: Graphene Nanoribbon Transistors Transport Characteristics of aGNRFETs 42.6.5 Example 2: Silicon Nanowire FETs 42.7 Conclusions and Outlook References 43 Quantum Transport in the Phase Space, the Wigner Equation 43.1 Why a Quantum Theory in the Phase Space? 43.2 An Introduction to Standard Quantum Mechanics 43.3 Quantum Mechanics in the Phase Space 43.3.1 The Single-Body Problem The Single-Body Wigner Transport Equation Scattering Effects: The Wigner-Boltzmann Transport Equation (WBTE) 43.3.2 The Many-Body Problem 43.3.3 The Many-Body Liouville von Neumann Equation The Many-Body Wigner Equation Indistinguishable Fermions 43.3.4 The Moyal Mathematical Formalization 43.3.5 The Weyl Map and the Equations of Motion 43.3.6 Admissible States in Phase Space 43.4 Monte Carlo Methods to Simulate the Single-Body Wigner Equation 43.4.1 The Affinity Method 43.4.2 Affinity Evolution and Monte Carlo Algorithm 43.4.3 Conservation of Affinity and Pseudo-Particle Injection 43.4.4 Basic Validation for Typical Cases 43.4.5 Application of the Affinity Method to Electronic Devices: The Resonant Tunneling Diode 43.4.6 Electrical Characteristics 43.4.7 Decoherence and Quantum/Semiclassical Transition 43.4.8 The Signed Particle Method 43.5 Monte Carlo Methods to Simulate the Many-Body Wigner Equation 43.5.1 The Density Functional Theory 43.5.2 The Wigner Density Functional Theory 43.5.3 The Wigner Monte Carlo Method for Many-Body Systems 43.5.4 Signed Particle Method 43.6 Neural Networks to Compute the Kernel References 44 The Nonequilibrium Green Function (NEGF) Method 44.1 Introduction 44.1.1 Decoupling NEGF from MBPT 44.1.2 Outline 44.2 NEGF Equations 44.3 NEGF Equations from One-Electron Schrödinger Equation 44.3.1 NEGF Eqs.(44.1) and (44.2) 44.3.2 NEGF Eq.(44.3) 44.4 A Simple Example 44.4.1 Hamiltonian H 44.4.2 Self-Energy Due to Contacts 44.4.3 Inscattering from Contacts 44.4.4 Current 44.4.5 Dephasing Interactions 44.4.6 Diffusive Spin Transport Using NEGF 44.4.7 Application to Superconducting Devices 44.5 Frequently Asked Questions 44.5.1 Shouldn't We Also Consider the Poisson Equation for Modeling Real Devices? 44.5.2 Can You Arbitrarily Designate the Ends as Contacts? 44.5.3 Does NEGF Give the Correct Coherent and Semiclassical Limits? 44.5.4 How Is This Related to the Kubo Formalism? Isn't It a Problem to Have Separate Electrochemical Potentials in a Single System? Doesn't the Kubo Formula Use a Single Electrochemical Potential? Can't You Have Equilibrium Currents with a Single Electrochemical Potential? 44.5.5 Isn't the Flow of Electricity Essentially a Many-Body Process? Are Many-Body Effects Irrelevant in Transport Experiments? Would NEGF Be Suitable for Describing Such Effects? 44.5.6 How Can We Teach NEGF Without Advanced Quantum Statistical Mechanics? 44.5.7 But Is This the Real NEGF? 44.5.8 Contacting Schrödinger References 45 Tight-Binding Models, Their Applications to Device Modeling, and Deployment to a Global Community 45.1 Nanodevice Characteristics 45.2 Nanodevice Modeling Approaches 45.3 Empirical Tight-Binding Method 45.3.1 Bases for the Hamiltonian 45.3.2 Parameter Fitting 45.3.3 Strain 45.3.4 Consequences of Discreteness and Incompleteness 45.3.5 Effective-Mass Formula 45.3.6 Localized-Orbital Representations 45.3.7 Electromagnetic Coupling Hamiltonian 45.4 Interfaces and Transport 45.4.1 Complex Bands 45.4.2 Transmission Calculations with Transfer Matrices: Numerical Stability 45.4.3 Direct Transmission Methods 45.4.4 DFT-TB and Nanodevice Modeling 45.5 Transport with Green Functions 45.6 Large-Scale Numerical Aspects 45.6.1 Hamiltonian Matrix Structures and Scaling for Closed Systems 45.6.2 Scaling Issues with Open Boundary Conditions 45.6.3 Quantum Transport: Parallel Computing Scaling 45.6.4 Surface Passivation 45.7 Applications 45.7.1 Quantum Dots: Closed Systems 45.7.2 Nanowire Electronic Structure: Quasi-Periodic in 1D and Closed Systems in 2D 45.7.3 Ballistic Transport from Nanowire Dispersions with the Top-of-the-Barrier Model 45.7.4 Full Quantum Transport in “Long” 15 nm Nanowires: 3D Representation 45.7.5 Full Quantum Transport Versus an Analytical Model in “Long” 15-nm Nanowires 45.7.6 Full Quantum Transport in Short 5-nm Nanowires: 3D Representation 45.7.7 Convergence Issues in High-Bias Coherent Transport Simulations 45.7.8 Short Channel Devices: A New Design Paradigm with New Requirements 45.8 Beyond Device Physics Advancements: Reaching the World 45.9 Conclusions References Index