High-Performance and High-Speed Pipelined ADCs

Description

This book discusses the theoretical foundations and design techniques needed to effectively design high-speed (multi-GS/s) and high-performance pipelined ADCs, which play a critical role in the signal chain of various systems. Readers will be walked through the design and analysis of pipelined ADCs and their topologies, and will learn both theoretical and practical design details that will enable them to explore and build these data converters.  The author also presents details on various aspects of pipelined ADCs and their impact on the ADC speed and performance, with a focus on the input buffer and sampling network, the reference amplifier, comparators and their impact on ADC error rate and high-frequency performance, and mismatch estimation and correction.   Contents List of Figures 1 Introduction [DELETE] 1.1 Overview 1.1.1 Chapter Organization 1.2 A Quick Overview of Some ADC Basics 1.2.1 ADC Sampling 1.2.2 ADC Quantization 2 Overview of Pipelined ADCs [DELETE] 2.1 Searching for the Analog Estimate 2.2 Elements of a Pipelined ADC 2.2.1 The Sub-ADC 2.2.2 The DAC 2.2.3 The Summation Node 2.2.4 The Gain Element 2.3 Cascading Multiple Stages 2.3.1 Combining the Sub-ADC Outputs 2.3.2 Impact of Gain on Input-Referred Noise 2.3.3 Impact of Gain on Power 2.4 Pipelined ADC Architectural Artifacts 2.4.1 Impact of Non-ideal Sub-ADCs 2.4.2 Impact of Non-ideal DACs 2.4.3 Impact of Non-ideal Gain Elements 2.5 Impact on ADC INL 2.5.1 Extracting Nonlinearity Plots 2.5.2 Example Nonlinearity Plots 3 Pipelined ADC Topologies [DELETE] 3.1 Switched-Capacitor Topologies 3.1.1 Impact of Capacitor Mismatch 3.1.2 MDAC Switch Configurations 3.1.3 Timing Configuration 3.2 Alternative Switched-Capacitor Topologies 3.2.1 Flip-Around Topology 3.2.2 Separate DAC Capacitors 4 Frontend Sampling Networks [DELETE] 4.1 Frontend Input Buffer 4.1.1 Design Factors 4.2 Input Buffer Implementations 4.2.1 The Emitter Follower 4.2.2 The Source Follower 4.2.3 Alternative Input Buffer Implementations 4.3 Sampling Switches 4.3.1 Track Phase Distortion 4.4 Sub-ADC Sampling Network 4.4.1 Without a Frontend Track-and-Hold 4.4.2 Impact of Bandwidth Mismatch 4.5 A Buffer-Less Frontend 4.5.1 Introducing a Reset Phase 5 Comparator Design [DELETE] 5.1 Comparator Metastability 5.1.1 Metastability Rate 5.1.2 First-Order Comparator Model 5.2 Calculating the ADC Error Rate 5.2.1 Impact of Noise on Code Error Rate 5.2.2 ADC Error Rate Analysis 5.2.3 Simulating and Measuring Error Rates 5.3 Impact of Impulse Sensitivity Function 5.3.1 Comparator Impulse Sensitivity Function 5.3.2 Simulating the Impulse Sensitivity Function 5.3.3 Mapping the ISF to ADC Performance 6 Reference Generation [DELETE] 6.1 Reference Amplifier Options 6.1.1 Reference Error Modeling 6.2 Signal-Dependent Response 6.2.1 Examples of Signal-Dependent Charge 6.2.2 Generalized Charge Analysis 6.2.3 Mitigation Techniques 6.3 Impact of Reference Noise 6.3.1 Examples of Signal-Dependent Noise 6.3.2 Generalized Noise Analysis 7 Correcting Pipelined ADC Errors 7.1 Error Correction 7.1.1 DAC Error Correction 7.1.2 Gain Error Correction 7.2 Error Estimation 7.2.1 Intuition Behind Error Estimation 7.2.2 Estimation Example 7.2.3 Matrix-Based Estimation