ENGLISH

Fast Simulation of Computer Architectures

By Thomas M. Conte , Charles E. Gimarc (auth.) , Charles E. Gimarc (eds.)

Book information

Publisher
Springer US
Year
1995
ISBN
978-1-4613-6002-5, 978-1-4615-2361-1
DOI
10.1007/978-1-4615-2361-1
Language
english
Format
PDF
Filesize
17 MB (17488462 bytes)
Edition
1
Pages
244\248
Orientation
yes
Scanned
yes
Time added
2013-08-01 04:00:00
Processor Architectures; Computer Systems Organiza

Description

Chapters in Fast Simulation of Computer Architectures cover topics such as how to collect traces, emulate instruction sets, simulate microprocessors using execution-driven techniques, evaluate memory hierarchies, apply statistical sampling to simulation, and how to augment simulation with performance bound models. The chapters have been written by many of the leading researchers in the area, in a collaboration that ensures that the material is both coherent and cohesive. Audience: Of tremendous interest to practising computer architect designers seeking timely solutions to tough evaluation problems, and to advanced upper division undergraduate and graduate students of the field. Useful study aids are provided by the problems at the end of Chapters 2 through 8.

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