3D IC Integration and Packaging (Electronics)

Description

Publisher's Note: Products purchased from Third Party sellers are not guaranteed by the publisher for quality,  authenticity, or access to any online entitlements included with the product. A comprehensive guide to 3D IC integration and packaging technology 3D IC Integration and Packaging fully explains the latest microelectronics techniques for increasing chip density and maximizing performance while reducing power consumption. Based on a course developed by its author, this practical guide offers real-world problem-solving methods and teaches the trade-offs inherent in making system-level decisions. Explore key enabling technologies such as TSV, thin-wafer strength measurement and handling, microsolder bumping, redistribution layers, interposers, wafer-to-wafer bonding, chip-to-wafer bonding, 3D IC and MEMS, LED, and complementary metal-oxide semiconductor image sensors integration. Assembly, thermal management, and reliability are covered in complete detail. 3D IC Integration and Packaging covers: • 3D integration for semiconductor IC packaging • Through-silicon vias modeling and testing • Stress sensors for thin-wafer handling and strength measurement • Package substrate technologies • Microbump fabrication, assembly, and reliability • 3D Si integration • 2.5D/3D IC integration • 3D IC integration with passive interposer • Thermal management of 2.5D/3D IC integration • Embedded 3D hybrid integration • 3D LED and IC integration • 3D MEMS and IC integration • 3D CMOS image sensors and IC integration • PoP, chip-to-chip interconnects, and embedded fan-out WLP Cover Title Page Copyright Page Contents Preface Acknowledgments 1 3D Integration for Semiconductor IC Packaging 1.1 Introduction 1.2 3D Integration 1.3 3D IC Packaging 1.4 3D Si Integration 1.5 3D IC Integration 1.5.1 Hybrid Memory Cube 1.5.2 Wide I/O DRAM and Wide I/O 2 1.5.3 High Bandwidth Memory 1.5.4 Wide I/O Memory (or Logic-on-Logic) 1.5.5 Passive Interposer (2.5D IC Integration) 1.6 Supply Chains before the TSV Era 1.6.1 FEOL (Front-End-of-Line) 1.6.2 BEOL (Back-End-of-Line) 1.6.3 OSAT (Outsourced Semiconductor Assembly and Test) 1.7 Supply Chains for the TSV Era—Who Makes the TSV? 1.7.1 TSVs Fabricated by the Via-First Process 1.7.2 TSVs Fabricated by the Via-Middle Process 1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process 1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process 1.7.5 How About the Passive TSV Interposers? 1.7.6 Who Wants to Fabricate the TSV for Passive Interposers? 1.7.7 Summary and Recommendations 1.8 Supply Chains for the TSV Era—Who Does the MEOL, Assembly, and Test? 1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process 1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process 1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process 1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers 1.8.5 Summary and Recommendations 1.9 CMOS Images Sensors with TSVs 1.9.1 Toshiba's Dynastron™ 1.9.2 STMicroelectronics' VGA CIS Camera Module 1.9.3 Samsung's S5K4E5YX BSI CIS 1.9.4 Toshiba's HEW4 BSI TCM5103PL 1.9.5 Nemotek's CIS 1.9.6 SONY's ISX014 Stacked Camera Sensor 1.10 MEMS with TSVs 1.10.1 STMicroelectronics' MEMS Inertial Sensors 1.10.2 Discera's MEME Resonator 1.10.3 Avago's FBAR MEMS Filter 1.11 References 2. Through-Silicon Vias Modeling and Testing 3. Stress Sensors for Thin-Wafer Handling and Strength Measurement 4. Package Substrate Technologies 5. Microbumps: Fabrication, Assembly, and Reliability 6. 3D Si Integration 7. 2.5D/3D IC Integration 8. 3D IC Integration with Passive Interposer 9. Thermal Management of 2.5D/3D IC Integration 10. Embedded 3D Hybrid Integration 11. 3D LED and IC Integration 12. 3D MEMS and IC Integration 13. 3D CMOS Image Sensor and IC Integration 14. 3D IC Packaging Index