VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability : 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers

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This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016. The 11 papers included in the book were carefully reviewed and selected from the 36 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design. Read more... Abstract: This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016. The 11 papers included in the book were carefully reviewed and selected from the 36 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design Front Matter ....Pages I-XIV Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures (Xueqing Li, Kaisheng Ma, Sumitha George, John Sampson, Vijaykrishnan Narayanan)....Pages 1-23 Logic with Unipolar Memristors – Circuits and Design Methodology (Nimrod Wald, Elad Amrani, Avishay Drori, Shahar Kvatinsky)....Pages 24-40 Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors (Maedeh Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram)....Pages 41-59 Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits (Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino)....Pages 60-82 Digital Hardware Design Based on Metamodels and Model Transformations (Johannes Schreiner, Wolfgang Ecker)....Pages 83-107 Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings (Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione)....Pages 108-129 Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs (Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sanchez, Federico Venini)....Pages 130-151 Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping (Valentino Peluso, Roberto G. Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto)....Pages 152-172 Earth Mover’s Distance as a Comparison Metric for Analog Behavior (Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker)....Pages 173-191 Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO (Syed Mohsin Abbas, Chi-Ying Tsui)....Pages 192-212 A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA (Yanzhe Li, Kai Huang, Luc Claesen)....Pages 213-232 Back Matter ....Pages 233-233