The g m /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits: The semi-empirical and compact model approaches

Description

How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests. Front Matter....Pages i-xvi Sizing the Intrinsic Gain Stage....Pages 1-9 The Charge Sheet Model Revisited....Pages 11-24 Graphical Interpretation of the Charge Sheet Model....Pages 25-39 Compact Modeling....Pages 41-66 The Real Transistor....Pages 67-91 The Real Intrinsic Gain Stage....Pages 93-112 The Common-Gate Configuration....Pages 113-119 Sizing the Miller Op. Amp.....Pages 121-142 Back Matter....Pages 143-171