Beyond Binary Memory Circuits: Multiple-Valued Logic

Description

This book provides readers with an overview of the fundamental definitions and features of Multiple-Valued Logic (MVL). The authors include a brief discussion of the historical development of MVL technologies, while the main goal of the book is to present a comprehensive review of different technologies that are being explored to implement multiple-valued or beyond-binary memory circuits and systems. The discussion includes the basic features, prospects, and challenges of each technology, while highlighting the significant works done on different branches of MVL memory architecture, such as sequential circuits, random access memory, Flash memory, etc. Preface About the Subject About This Book Organization of the Book Acknowledgements Contents About the Authors Abbreviations List of Figures List of Tables 1 Background and Future of Multiple Valued Logic 1.1 Introduction 1.2 What is Multiple-Valued Logic 1.3 Computational Advantages of MVL System 1.4 Historical Background 1.5 Scopes of MVL Technology 1.5.1 Arithmetic Circuit Design 1.5.2 Memory Circuit Design 1.5.3 Quantum Computing 1.5.4 High-Speed Signaling 1.5.5 Cloud Based Computing Platform 1.5.6 Other Applications of MVL System 1.6 Challenges of MVL System 1.7 Future Direction 1.8 Conclusion References 2 Mathematical Representation of Multi Valued Logic 2.1 Definition and Signal Representation 2.2 Basic Algebraic Operators for MVL 2.3 Synthesis Technique of MVL 2.4 Conclusion References 3 Overview of Different Technologies for Multiple-Valued Memory 3.1 Planar MOSFET Technology 3.1.1 Operating Principle 3.1.2 Analysis 3.2 Silicon on Insulator (SOI) and Fin Field Effect Transistor (FinFET) 3.2.1 Fully Depleted Silicon-on-Insulator (FDSOI) 3.2.2 Fin Field Effect Transistor (FinFET) 3.2.3 Analysis 3.3 Resonant Tunneling Diode (RTD) Technology 3.3.1 Operating Principle 3.3.2 Analysis 3.4 Single Electron Transistor (SET) Technology 3.4.1 Operating Principle 3.4.2 Analysis 3.5 Carbon Based Technologies: CNTFET and GNRFET 3.5.1 Operating Principle 3.5.2 Analysis 3.6 Memristor 3.6.1 Operating Principle 3.6.2 Analysis 3.7 Magnetic Tunnel Junction (MTJ) 3.7.1 Operating Principle 3.7.2 Analysis 3.8 Neuron Metal Oxide Semiconductor (Neuron-MOS) 3.8.1 Operating Principle 3.8.2 Analysis 3.9 Conclusion References 4 MVL Sequential Circuits 4.1 Introduction 4.2 Ternary D-Latch 4.3 Ternary D Flip-Flop 4.3.1 Positive Edge Triggered D Flip-Flap-Flop 4.4 Analysis 4.5 Application of Ternary Sequential Circuits 4.6 Conclusion References 5 MVL Random Access Memory 5.1 Introduction 5.2 Static Random-Access Memory (SRAM) 5.2.1 Design 1 of a Ternary SRAM 5.2.2 Design 2 of a Ternary SRAM 5.2.3 Analysis 5.3 Dynamic Random-Access Memory (DRAM) 5.3.1 Design 1 a Ternary DRAM 5.3.2 Design 2 a Ternary DRAM 5.3.3 Analysis 5.4 Multi-level Dynamic Random-Access Memory (MLDRAM) 5.4.1 MLDRAM Design Proposed by Gillingham 5.4.2 Analysis 5.5 Conclusion References 6 MVL Flash Memory 6.1 Introduction 6.2 Floating Gate MOS (FGMOS) 6.3 ETOX Flash 6.4 NAND and NOR Flash Memory 6.5 Multi-level Memory Cell Concept 6.5.1 Working Principle of Multi-valued Flash Memory 6.5.2 Planar Versus Vertical NAND 6.6 Conclusion References 7 Ternary Content Addressable Memory 7.1 Introduction 7.2 Operation of Content-Addressable Memory (CAM) 7.3 Binary Versus Ternary CAM 7.4 Analysis References