Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Description

Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two. CMPs avoid these problems by filling up a processor die with multiple, relatively simpler processor cores instead of just one huge core. The exact size of a CMPs cores can vary from very simple pipelines to moderately complex superscalar processors, but once a core has been selected the CMPs performance can easily scale across silicon process generations simply by stamping down more copies of the hard-to-design, high-speed processor core in each successive chip generation. In addition, parallel code execution, obtained by spreading multiple threads of execution across the various cores, can achieve significantly higher performance than would be possible using only a single core. While parallel threads are already common in many useful workloads, there are still important workloads that are hard to divide into parallel threads. The low inter-processor communication latency between the cores in a CMP helps make a much wider range of applications viable candidates for parallel execution than was possible with conventional, multi-chip multiprocessors; nevertheless, limited parallelism in key applications is the main factor limiting acceptance of CMPs in some types of systems. book.pdf......Page 0 The Case for CMPs......Page 9 A NEW APPROACH: THE CHIP MULTIPROCESSOR (CMP)......Page 13 The Application Parallelism Landscape......Page 14 A Simple Example: Superscalar vs. CMP......Page 16 Simulation Results......Page 20 This Book: Beyond Basic CMPs......Page 25 Improving Throughput......Page 28 The Need for Multithreading within Processors......Page 32 Maximizing the Number of Cores on the Die......Page 33 Example 1: The Piranha Server CMP......Page 34 Example 2: The Niagara Server CMP......Page 42 Example 3: The Niagara 2 Server CMP......Page 52 Simple Core Limitations......Page 55 Simulating a Large Design Space......Page 56 Choosing Design Datapoints......Page 59 Results......Page 61 Discussion......Page 62 Improving Latency Automatically......Page 68 PSEUDO-PARALLELIZATION: ``HELPER'' THREADS......Page 70 AUTOMATED PARALLELIZATION USING THREAD-LEVEL SPECULATION (TLS)......Page 71 The Base Hydra Design......Page 78 Adding TLS to Hydra......Page 79 Using Feedback from Violation Statistics......Page 88 Performance Analysis......Page 92 Completely Automated TLS Support: The JRPM System......Page 96 Concluding Thoughts on Automated Parallelization......Page 107 Improving Latency Using Manual Parallel Programming......Page 110 USING TLS SUPPORT AS TRANSACTIONAL MEMORY......Page 112 An Example: Parallelizing Heapsort Using TLS......Page 113 Parallelizing SPEC2000 with TLS......Page 122 TRANSACTIONAL COHERENCE AND CONSISTENCY (TCC): MORE GENERALIZED TRANSACTIONAL MEMORY......Page 124 TCC HARDWARE......Page 126 TCC Software......Page 129 TCC Performance......Page 135 MIXING TRANSACTIONAL MEMORY AND CONVENTIONAL SHARED MEMORY......Page 144 A Multicore World: The Future of CMPs......Page 148