Nanoelectronics for Next-Generation Integrated Circuits

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Cover Half Title Title Page Copyright Page Dedication Table of Contents Preface Acknowledgments List of Contributors About the Editor Chapter 1 Emerging Graphene-Based Electronics: Properties to Potentials 1.1 Introduction 1.2 Simulation Methodology for Self-Healing Studies 1.3 Self-Healing of Pristine and Pre-Existing Defective Graphene Sheets 1.4 Possible Application of the Self-Healing Phenomenon of Graphene 1.5 Magnetic Phase Transitions 1.6 Conclusions References Chapter 2 Models for Modern Spintronics Memories with Layered Magnetic Interfaces 2.1 Introduction 2.2 Advanced Spintronics Memories 2.2.1 Modern Spintronics Memories 2.2.2 VCMA Model 2.2.3 The Rashba SOI Model 2.3 Magnetic Layered Interfaces for TST-MRAM 2.3.1 HM/FM Interfacial Modulation for Strong PMA 2.3.2 PMA in Cobalt-Dependent Multilayers 2.3.3 PMA in FM/Co-Fe-B/MgO Structures 2.3.4 PMA in HM/CoFeB/NM/MgO Structures 2.4 Future Trends in Spintronics Memory References Chapter 3 Evaluation of Magnetic Anisotropy via Intrinsic Spin Infusion 3.1 Introduction 3.2 Spin Infusion in MTJ and Effective Torque 3.2.1 Spin Infusion in MTJ 3.2.2 Spin Torque 3.2.2.1 Magnetic Field Torque 3.2.2.2 Damping Torque 3.2.2.3 Spin-Transfer Torque 3.3 Spin-Infusion Magnetic Switching 3.3.1 Expansion of the Precession 3.3.2 Cylindrical Pillar With Uniaxial Anisotropy 3.3.3 Linearized LLG Equation 3.4 Other Techniques in Spin-Dependent Computation References Chapter 4 Quantum-Dot Cellular Automata (QCA) Nanotechnology for Next-Generation Systems 4.1 Introduction 4.2 Background 4.3 Full Adder Using QCA Nanotechnology 4.4 Comparison Analysis 4.5 Conclusion References Chapter 5 An Overview of Nanowire Field-Effect Transistors for Future Nanoscale Integrated Circuits 5.1 ZnO/CuO/PbS NW FETs 5.2 III-V NANOWIRE FETs 5.3 III-V NANOWIRE TFETs 5.4 JL NW FETs 5.5 NW NCFETs 5.6 Reconfigurable NW FETs 5.7 Reliability Issues in NW FETs 5.8 Si NW FETs 5.9 Summary References Chapter 6 Investigation of Tunnel Field-Effect Transistors (TFETs) for Label-Free Biosensing 6.1 Introduction 6.2 Sensitivity Analysis 6.3 Case Study 1: Dual-Gate Source Electrode Dielectrically Modulated TFETs for Biosensing Application 6.4 Case Study 2: Source Electrode Hetero-Material Dielectrically Modulated TFETs for Biosensing Application 6.5 Conclusions References Chapter 7 Analog and Linearity Analysis of Vertical Nanowire TFET 7.1 Introduction 7.2 Types of Devices 7.3 Results and Discussion 7.3.1 Linear Parameters Analysis 7.3.2 Analog Parameters Analysis 7.4 Conclusions References Chapter 8 Effects of Variation in Gate Material on Enhancement Mode P-GaN AlGaN/GaN HEMTs 8.1 Introduction 8.2 Power Devices 8.3 Gallium Nitride 8.4 High Electron Mobility Transistor (HEMT) 8.4.1 Conventional HEMT Structure 8.4.2 Source of Two-Dimensional Electron Gas 8.4.3 Band Diagram of a Conventional HEMT 8.4.4 Normally-Off HEMT 8.5 Simulation and Results 8.6 Conclusion 8.7 Future Scope References Chapter 9 Electrical Modeling of One Selector-One Resistor (1S-1R) for Mitigating the Sneak-Path Current in a Nano-Crossbar Array 9.1 Introduction to the RRAM Models and Their Potential Challenges 9.1.1 RRAM Technology – Background Studies and Current Research Development 9.1.2 RRAM Crossbar Array Formation and Sneak-Path Current 9.2 Methods to Mitigate Sneak-Path Current in RRAM Arrays 9.2.1 Associating a Selector Device With Memory Unit (1S-1R): A Literature Review 9.3 Implementation of an Electrical Model of Selector Device and RRAM Device 9.3.1 Electrical Modeling of a Selector Device 9.3.2 Electrical Model Implementation of a Pt/Ta2O5/TaOx/Pt RRAM Device Incorporating the Current Through the Outside of the Conduction Filament (OCF) 9.4 Integrated Modeling of the Proposed Selector Model with the RRAM Model 9.4.1 Analysis and Results 9.5 Formation and Sneak-Path Current Measurement of 2 × 2 CBA of 1S-1R With a Pt/Ta2O5/TaOx/TiO2/Pt Selector and Pt/Ta2O5/TaOx/Pt RRAM References Chapter 10 SRAM: An Essential Part of Integrated Circuits 10.1 Introduction 10.2 Application Windows 10.2.1 IoT-Enabled Wireless Sensor Networks 10.2.2 Multimedia Applications 10.2.3 High-Performance Processors 10.3 Conventional SRAM Cell 10.3.1 Device Sizing Strategy for Functional 6T SRAM Cell 10.3.2 Memory Architecture 10.4 Major Design Challenges of SRAM Memory for Modern Integrated Circuits 10.4.1 Process Variation Effects 10.4.2 Temperature Variation Effect on Read and Write Ability 10.4.3 Read/Write Conflict and Read-Decoupled 8T SRAM Cell 10.4.4 Read Current to Leakage Current Ratio (IRead/ILeak) 10.4.5 Performance and Stability Trade-off 10.4.6 Half-Select Issue 10.5 Various Approaches to Solve the Design Issues of Conventional Bit Cells 10.6 Low-Voltage Highly Stable 12T SRAM Cell Design for WSNs 10.7 In-Memory Computing for the Modern AI Edge Devices and its Challenges 10.7.1 Key Challenges of In-Memory Computing 10.8 Conclusion References Chapter 11 Implementation of 512-bit SRAM Tile Using the Lector Technique for Leakage Power Reduction 11.1 Introduction 11.2 Literature Review 11.3 Static Random-Access Memory (SRAM) – Architecture and Operation 11.3.1 SRAM Architecture 11.3.2 Read Operation 11.3.3 Write Operation 11.4 The Lector Technique 11.4.1 Applying the Lector Technique to SRAM 11.5 Results and Discussion 11.6 Conclusion Acknowledgment References Chapter 12 Characterization of Stochastic Process Variability Effects on Nano-Scale Analog Circuits 12.1 Introduction 12.2 Background Concepts 12.2.1 Randomness of Circuit Parameters and Circuit Performance Parameters 12.2.2 Major Sources of Stochastic Process Variability 12.2.2.1 Random Discrete Dopant Effect 12.2.2.2 Line Edge/Line Width Roughness 12.2.2.3 Oxide Thickness Variations 12.2.3 Numerical Measures of Descriptive Statistics 12.3 Statistical Characterization Methodology for Stochastic Process Variability 12.3.1 Identification of the Berkeley Simulation IGFET Model (BSIM) Compact Model Parameters to Stochastic Process Variabilities 12.3.2 Sample Design 12.3.3 Data Collection Through Designed Experiment 12.3.4 Sample Statistics and Measures 12.4 Implementation of the Methodology 12.4.1 Systematic Process Variability 12.4.2 Stochastic Process Variability 12.5 Application Example: Current Reference Circuit for Ultra-Low Power Analog Applications 12.5.1 Characterization of Systematic Process Variability 12.5.2 Characterization of Stochastic Process Variability 12.5.2.1 Oxide Thickness Variations 12.5.2.2 Threshold Voltage Variations 12.6 Conclusion Acknowledgment References Chapter 13 Versatile Single Input Single Output Filter Topology Suitable for Integrated Circuits 13.1 Introduction 13.2 Theoretical Details Of The Proposed Filter 13.2.1 Working Principle of EXCCII 13.2.2 Proposed SISO filter topology 13.3 Filter Functionalities Derived From Proposed SISO Filter Topology 13.3.1 First-Order AP Filter 13.3.2 Second-Order AP Filter and Notch Filter 13.4 Non-Ideal Analysis of the Proposed SISO Filter Topology 13.5 Simulation Results 13.6 Conclusion References Chapter 14 Secured Integrated Circuit (IC/IP) Design Flow 14.1 Introduction 14.2 Discussion of Contemporary Approaches 14.3 Structural Obfuscation of IP Cores 14.3.1 The Basic Definition and Threat Model of Structural Obfuscation 14.3.2 Why Performing SO during HLS is Beneficial? 14.3.3 Description of Multi-Stage Structural Obfuscation Process (Sengupta et al., 2017) 14.4 Functional Obfuscation of DSP IP Cores 14.4.1 Reverse Engineering Attacks during the Various Stages of IP Core Design 14.4.2 Attack Scenarios 14.4.3 Functional Obfuscation Approach for DSP Cores 14.4.4 Handling Attacks 14.5 Hardware Watermarking 14.5.1 Features of the Multi-Variable Watermarking Approach (Bhadauria And Sengupta, 2016) for Signature Insertion During High-Level Synthesis 14.5.2 Signature Encoding Mechanism in Multi-Variable Watermarking Approach (Bhadauria and Sengupta, 2016) 14.5.3 Process of Watermark Creation for an IP Core Using a Multi-Variable Signature (Bhadauria and Sengupta, 2016) 14.5.4 Motivation for Performing Design Space Exploration of an Optimal Watermark 14.5.5 Resolving Attacks and Ownership Problems through a Multi-Variable Watermark Approach (Bhadauria and Sengupta, 2016) 14.5.6 Properties/Metrics of Watermark Generated through Multi-Variable Watermarking Approach (Bhadauria and Sengupta, 2016) 14.6 Conclusion References Index