ENGLISH

A Guide to VHDL

Book information

Publisher
Springer US
Year
1992
ISBN
978-1-4757-2116-4, 978-1-4757-2114-0
DOI
10.1007/978-1-4757-2114-0
Language
english
Format
PDF
Filesize
11 MB (11816855 bytes)
Pages
XXIII, 314 p.\308
Orientation
yes
Scanned
yes
Time added
2013-08-01 04:00:00

Description

A Guide to VHDL is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises invluded in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL can be used as a primer, since its contents are appropriate for an introductory course in VHDL.

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