Mismatch and Noise in Modern Ic Processes

Description

Component variability, mismatch, and various noise effects are major contributors to design limitations in most modern IC processes. Mismatch and Noise in Modern IC Processes examines these related effects and how they affect the building block circuits of modern integrated circuits, from the perspective of a circuit designer. Variability usually refers to a large scale variation that can occur on a wafer to wafer and lot to lot basis, and over long distances on a wafer. This phenomenon is well understood and the effects of variability are included in most integrated circuit design with the use of corner or statistical component models. Mismatch, which is the emphasis of section I of the book, is a local level of variability that leaves the characteristics of adjacent transistors unmatched. This is of particular concern in certain analog and memory systems, but also has an effect on digital logic schemes, where uncertainty is introduced into delay times, which can reduce margins and introduce 'race' conditions. Noise is a dynamic effect that causes a local mismatch or variability that can vary during operation of a circuit, and is considered in section II. Noise can be the result of atomic effects in devices or circuit interactions, and both of these are discussed in terms of analog and digital circuitry. Table of Contents: Part I: Mismatch / Introduction / Variability and Mismatch in Digital Systems / Variability and Mismatch in Analog Systems I / Variability and Mismatch in Analog Systems II / Lifetime-Induced Variability / Mismatch in Nonconventional Processes / Mismatch Correction Circuits / Part II: Noise / Component and Digital Circuit Noise / Noise Effects in Digital Systems / Noise Effects in Analog Systems / Circuit Design to Minimize Noise Effects / Noise Considerations in SOI Mismatch and Noise in Modern IC Processes......Page 1 Keywords......Page 4 Preface......Page 5 Contents......Page 7 Part I Mismatch......Page 11 1.2 NMOS OPERATION......Page 13 1.2.1 Linear Region......Page 14 1.2.4 Subthreshold Mode (Cutoff)......Page 15 1.4 VARIABILITY AND MISMATCH......Page 16 1.4.1 How Do They Happen?......Page 17 1.5.1 Random Dopant Fluctuation......Page 18 1.5.4 Temperature-Induced Variability/Mismatch......Page 19 1.6 CMOS GATES......Page 20 1.7 RING OSCILLATORS AND GATE CHAINS......Page 22 2.1 EFFECT OF INTERCONNECT......Page 23 2.3 DIGITAL CORRELATION......Page 24 2.3.1 Defining Idtran Voltage......Page 26 2.4.1 Variability and Mismatch Parameters......Page 27 2.5 VERIFYING RANDOMNESS......Page 31 3.1 CURRENT MIRRORS......Page 33 3.2 GLOBAL VARIATION......Page 34 3.3 CASCODE CURRENT MIRROR......Page 39 3.4 WILSON CURRENT MIRROR......Page 42 4.1 OPERATIONAL AMPLIFIER......Page 43 4.1.1 Input Pair Matching......Page 44 4.2.1 Open-Loop Gain......Page 45 4.2.3 DC Imperfections in Op-Amps......Page 46 4.3.1 Nonzero Output Resistance......Page 47 4.3.2 Input Bias Current......Page 48 4.3.3 Input Offset Voltage......Page 49 4.4 COMMON MODE GAIN......Page 50 4.5 REDUCING THE COMMON MODE EFFECT......Page 51 4.7 AC OP-AMP NONLINEARITIES......Page 53 4.7.1 Mismatch Issues in SRAM......Page 55 4.7.2 Mismatch and Variability......Page 59 5.1.2 Negative Bias Temperature Instability......Page 61 5.2 EFFECTS ON CIRCUITS OF NBTI: CURRENT MIRRORS......Page 64 5.3 EFFECTS ON CIRCUITS OF NBTI: OP-AMPS......Page 65 5.4 EFFECTS ON CIRCUITS OF NBTI: STATIC RANDOM ACCESS MEMORY......Page 66 6.1 WHAT IS SOI?......Page 69 6.1.1 Partially Depleted SOI......Page 70 6.1.2 Fully Depleted SOI (FinFET)......Page 74 6.1.3 Considerations That Affect Both FDSOI and PDSOI......Page 75 6.2 CIRCUIT EFFECTS OF HIGH-TEMPERATURE LEAKAGE......Page 76 6.3 SELF-HEATING AND DISSIPATION PROBLEMS WITHIN A DEVICE......Page 77 6.3.2 Transient or AC Thermal Coupling......Page 78 6.4 DIGITAL CIRCUITS IN SOI......Page 79 6.5.1 Current Mirror: Kink Region Operation......Page 80 6.5.2 Operational Amplifier......Page 82 6.5.3 Operational Transconductance Amplifier......Page 83 7.1 TRIMMING METHODS......Page 85 7.1.2 E-Fuse Circuit......Page 86 7.1.4 E-Fuse Sense Circuit......Page 88 7.1.6 EPROM/EEPROM......Page 90 7.1.7 FeRAM Cell Design......Page 91 7.2.1 Frequency......Page 93 7.2.3 Mismatch Trimming......Page 95 7.3 CASE STUDY: POWER IC DESIGN FOR TESTABILITY......Page 97 Part II Noise......Page 99 8.1.3 Shot Noise......Page 101 8.2 PHYSICAL SOURCES OF NOISE......Page 102 8.3.1 1/f Noise BSIM Modeling......Page 103 8.4 JITTER AND NOISE IN DIGITAL CIRCUITS: CIRCUIT EFFECTS......Page 104 9.1 NOISE IN RING OSCILLATORS......Page 109 9.2 DYNAMIC LOGIC......Page 110 9.3 INPUT PROTECTION......Page 113 10.1 SYSTEM ON A CHIP......Page 119 10.2 NOISE IN AN OP-AMP......Page 120 10.2.1 Effect of Noise Due to Two Cascaded Amplifiers......Page 122 10.3 LC OSCILLATOR......Page 123 10.4 STATIC RANDOM ACCESS MEMORY......Page 125 10.4.1 Radiation Hardness in Static Random Access Memory......Page 126 11.1 GUARD RINGING......Page 129 11.2 NOISE SUPPRESSION THROUGH INTERCONNECT......Page 130 11.2.2 Substrate Noise Reduction......Page 131 11.4.1 Smart Sensors......Page 133 11.4.2 Operational Amplifiers......Page 134 12.1 SUBSTRATE COUPLING......Page 137 12.2 SUBSTRATE CAPACITANCE/SUPPLY CAPACITANCE......Page 138 12.3 RADIATION EFFECTS......Page 139 12.4 SOI COMPONENT NOISE......Page 140 References......Page 143 Index......Page 145 Biography......Page 149