VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers

Description

This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification. Front Matter ....Pages I-XXI Front Matter ....Pages 1-1 Flexible Composite Galois Field \(GF((2^m)^2)\) Multiplier Designs (M. Mohamed Asan Basiri, Sandeep K. Shukla)....Pages 3-14 Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions (Manan Mewada, Mazad Zaveri, Anurag Lakhlani)....Pages 15-23 VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter (Mohd. Tasleem Khan, Shaik Rafi Ahamed)....Pages 24-35 Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder (K. Dheepika, K. S. Jevasankari, Vippin Chandhar, Binsu J. Kailath)....Pages 36-47 Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm (Pravin Zode, R. B. Deshmukh, Abdus Samad)....Pages 48-55 Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices (Jatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra)....Pages 56-61 A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications (Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury)....Pages 62-68 A Framework for Branch Predictor Selection with Aggregation on Multiple Parameters (Moumita Das, Ansuman Banerjee, Bhaskar Sardar)....Pages 69-74 FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT (Thilagavathy R, Susmitha Settivari, Venkataramani B, Bhaskar M)....Pages 75-80 Front Matter ....Pages 81-81 Low Voltage, Low Power Transconductor for Low Frequency \(G_m\)-C Filters (Hanumantha Rao G., Rekha S.)....Pages 83-92 An Improved Highly Efficient Low Input Voltage Charge Pump Circuit (Naresh Kumar, Raja Hari Gudlavalleti, Subash Chandra Bose)....Pages 93-102 A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage (Pallavi Darji, Chetan Parikh)....Pages 103-114 Characterization and Compensation Circuitry for Piezo-Resistive Pressure Sensor to Accommodate Temperature Induced Variation (M. Santosh, Anjli Bansal, Jitendra Mishra, K. C. Behra, S. C. Bose)....Pages 115-126 FEM Based Device Simulator for High Voltage Devices (Ashok Ray, Gaurav Kumar, Sushanta Bordoloi, Dheeraj Kumar Sinha, Pratima Agarwal, Gaurav Trivedi)....Pages 127-135 Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology (Sushma Srivastava, S. S. Rathod)....Pages 136-143 A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator (Vivek Tyagi, M. S. Hashmi, Ganesh Raj, Vikas Rana)....Pages 144-152 Front Matter ....Pages 153-153 Deterministic Shift Power Reduction in Test Compression (Kanad Basu, Rishi Kumar, Santosh Kulkarni, Rohit Kapur)....Pages 155-167 Pseudo-BIST: A Novel Technique for SAR-ADC Testing (Yatharth Gupta, Sujay Deb, Vikrant Singh, V. N. Srinivasan, Manish Sharma, Sabyasachi Das)....Pages 168-178 SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis (Rahul Bhattacharya, S. H. M. Ragamai, Subindu Kumar)....Pages 179-190 A Cost Effective Technique for Diagnosis of Scan Chain Faults (Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu, Ashok Suhag)....Pages 191-204 Multi-mode Toggle Random Access Scan to Minimize Test Application Time (Anshu Goel, Rohini Gulve)....Pages 205-216 Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors (Avishek Choudhury, Biplab K. Sikdar)....Pages 217-224 Front Matter ....Pages 225-225 Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs (Ashish Soni, Abhijit Umap, Nihar R. Mohapatra)....Pages 227-238 Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance (Satish Maheshwaram, Om Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas)....Pages 239-248 Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor (Ajay Singh, Rakhi Narang, Manoj Saxena, Mridula Gupta)....Pages 249-258 Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs (Japa Aditya, Vallabhaneni Harshita, Ramesh Vaddi)....Pages 259-269 An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation (Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar)....Pages 270-278 Investigation of TCADs Models for Characterization of Sub 16 nm In\(_{0.53}\)Ga\(_{0.47}\)As FinFET (J. Pathak, A. Darji)....Pages 279-286 Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography (Arindam Sinharay, Pranab Roy, Hafizur Rahaman)....Pages 287-295 Front Matter ....Pages 297-297 Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization (Sumanth Gudaparthi, Rahul Shrestha)....Pages 299-312 Performance-Enhanced \(d^2\)-LBDR for 2D Mesh Network-on-Chip (Anugrah Jain, Vijay Laxmi, Meenakshi Tripathi, Manoj Singh Gaur, Rimpy Bishnoi)....Pages 313-323 ACAM: Application Aware Adaptive Cache Management for Shared LLC (Sujit Kr Mahto, Newton)....Pages 324-336 Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs (N. S. Aswathy, R. S. Reshma Raj, Abhijit Das, John Jose, V. R. Josna)....Pages 337-344 Defeating HaTCh: Building Malicious IP Cores (Anshu Bhardwaj, Subir Kumar Roy)....Pages 345-353 Low Cost Circuit Level Implementation of PRESENT-80 S-BOX (S. Shanthi Rekha, P. Saravanan)....Pages 354-362 Front Matter ....Pages 363-363 Modeling and Analysis of Transient Heat for 3D IC (Subhajit Chatterjee, Surajit Kr. Roy, Chandan Giri, Hafizur Rahaman)....Pages 365-375 Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder (Mamata Panigrahy, Nirmal Chandra Behera, B. Vandana, Indrajit Chakrabarti, Anindya Sundar Dhar)....Pages 376-387 Metal-Oxide Nanostructures Designed by Glancing Angle Deposition Technique and Its Applications on Sensors and Optoelectronic Devices: A Review (Divya Singh)....Pages 388-397 Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics (Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi)....Pages 398-405 Enhancing Retention Voltage for SRAM (Ankit Rehani, Sujay Deb, Suprateek Shukla)....Pages 406-413 Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies (Anand Ilakal, Anuj Grover)....Pages 414-420 Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space (Neha Chaudhuri, Chandan Bandyopadhyay, Hafizur Rahaman)....Pages 421-426 Front Matter ....Pages 427-427 Delay and Frequency Investigations in Coupled MLGNR Interconnects (Manish Joshi, Koduri Teja, Ashish Singh, Rohit Dhiman)....Pages 429-440 LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits (Ambika Prasad Shah, Nandakishor Yadav, Santosh Kumar Vishvakarma)....Pages 441-451 Performance Analysis of OLED with Hole Block Layer and Impact of Multiple Hole Block Layer (Shubham Negi, Poornima Mittal, Brijesh Kumar)....Pages 452-462 Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular Tapered Y-Gate Geometry (Rakhi Narang, Mridula Gupta, Manoj Saxena)....Pages 463-473 A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18 \(\upmu \)m CMOS (Purvi Patel, Biswajit Mishra, Dipankar Nagchoudhuri)....Pages 474-486 A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications ( Swaati, Bishnu Prasad Das)....Pages 487-495 Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective (Vandana Kumari, Manoj Saxena, Mridula Gupta)....Pages 496-503 Front Matter ....Pages 505-505 A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform (Rourab Paul, Sandeep Kumar Shukla)....Pages 507-518 New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation (Naushad Ali, Bharat Garg)....Pages 519-532 FPGA-Based Smart Camera System for Real-Time Automated Video Surveillance (Sanjay Singh, Sumeet Saurav, Ravi Saini, Atanendu S. Mandal, Santanu Chaudhury)....Pages 533-544 Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects (B. Vandana, J. K. Das, S. K. Mohapatra, B. K. Kaushik)....Pages 545-556 Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video Processing (Puja Ghosh, P. Rangababu)....Pages 557-569 A Custom Designed RISC-V ISA Compatible Processor for SoC (Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Amrutur Bharadwaj)....Pages 570-577 Front Matter ....Pages 579-579 An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction (Jasmine Kaur Gulati, Bhanu Prakash, Sumit Darak)....Pages 581-593 Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs (Ayan Palchaudhuri, Anindya Sundar Dhar)....Pages 594-606 On Generation of Delay Test with Capture Power Safety (Rohini Gulve, Nihar Hage)....Pages 607-618 A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC (Prokash Ghosh, Jyotirmoy Ghosh)....Pages 619-627 Front Matter ....Pages 629-629 A 10 MHz, 42 ppm/\( ^{ \circ } {\text{C}} \), 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM (Vivek Tyagi, M. S. Hashmi, Ganesh Raj, Vikas Rana)....Pages 631-645 A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS (Antaryami Panigrahi, Abhipsa Parhi)....Pages 646-656 A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm Process (Mudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad)....Pages 657-666 Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL’s 0.18 µm CMOS Process (Munish Malik, Ajay Kumar, H. S. Jatana)....Pages 667-678 Front Matter ....Pages 679-679 Fast FPGA Placement Using Analytical Optimization (Sameer Pawanekar, Gaurav Trivedi)....Pages 681-693 A Dependability Preserving Fluid-Level Synthesis for Reconfigurable Droplet-Based Microfluidic Biochips (Arpan Chakraborty, Piyali Datta, Debasis Dhal, Rajat Kumar Pal)....Pages 694-706 Splitting and Transport of a Droplet with No External Actuation Force for Lab on Chip Devices (T. Pravinraj, Rajendra Patrikar)....Pages 707-717 Analytical Partitioning: Improvement over FM (Sameer Pawanekar, Gaurav Trivedi)....Pages 718-730 A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip (Rajul Bansal, Mahendra Kumar Jatav, Abhijit Karmakar)....Pages 731-736 Droplet Position Estimator for Open EWOD System Using Open Source Computer Vision (Vandana Jain, Vasavi Devarasetty, Rajendra Patrikar)....Pages 737-741 Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder (Rituparna Choudhury, P. Rangababu)....Pages 742-750 Front Matter ....Pages 751-751 A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection (Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita)....Pages 753-766 Translation Validation of Loop Invariant Code Optimizations Involving False Computations (Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri)....Pages 767-778 A Framework for Automated Feature Based Mixed-Signal Equivalence Checking (Antara Ain, Sayandeep Sanyal, Pallab Dasgupta)....Pages 779-791 xMAS Based Accurate Modeling and Progress Verification of NoCs (Surajit Das, Chandan Karfa, Santosh Biswas)....Pages 792-804 Faulty TSVs Identification in 3D IC Using Pre-bond Testing (Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri)....Pages 805-812 Back Matter ....Pages 813-815