Nanoscale CMOS

Description

This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future – in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices.    This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies.   It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs.  Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.Content: Chapter 1 Introduction to Part 1 (pages 1–21): D. Leadley, A. Dobbie, V. Shah and J. ParsonsChapter 2 Gate Stacks (pages 23–67): O. Engstrom, I. Z. Mitrovic, S. Hall, P. K. Hurley, K. Cherkaoui, S. Monaghan, H. D. B. Gottlob and M. C. LemmeChapter 3 Strained Si and Ge Channels (pages 69–126): D. Leadley, A. Dobbie, M. Myronov, V. Shah and E. ParkerChapter 4 From Thin Si/SiGe Buffers to SSOI (pages 127–156): S. Mantl and D. BucaChapter 5 Introduction to Schottky?Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration (pages 157–204): E. Dubois, G. Larrieu, R Valentin, N. Breil and F. DannevilleChapter 6 Introduction to Part 2 (pages 205–212): E. SangiorgiChapter 7 Modeling and Simulation Approaches for Gate Current Computation (pages 213–257): B. Majkusiak, P. Palestri, A. Schenk, A. S. Spinelli, C. M. Compagnoni and M. LuisierChapter 8 Modeling and Simulation Approaches for Drain Current Computation (pages 259–285): M. Vasicek, D. Esseni, C. Fiegna and T. GrasserChapter 9 Modeling of End of the Roadmap nMOSFET with Alternative Channel Material (pages 287–334): Q. Rafhay, R. Clerc, G. Ghibaudo, P. Palestri and L. SelmiChapter 10 NEGF for 3D Device Simulation of Nanometric Inhomogenities (pages 335–380): A. Martinez, A. Asenov and M. PalaChapter 11 Compact Models for Advanced CMOS Devices (pages 381–442): B. Iniguez, F. Lime, A. Lazaro and T. A. FjeldlyChapter 12 Beyond CMOS (pages 443–470): G. Iannaccone, G. Fiori, S. Reggiani and M. PalaChapter 13 Introduction to Part 3 (pages 471–474): D. FlandreChapter 14 Accurate Determination of Transport Parameters in Sub?65 nm MOS Transistors (pages 475–544): M. Mouis and G. GhibaudoChapter 15 Characterization of Interface Defects (pages 545–573): P. Hurley, O. Engstrom, D. Bauza and G. GhibaudoChapter 16 Strain Determination (pages 575–601): A. O'Neill, S. Olsen, P. Dobrosz, R. Agaiby and Y. TsangChapter 17 Wide Frequency Band Characterization (pages 603–638): D. Flandre, J.?p. Raskin and V. Kilchytska