ENGLISH

A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof

By Silvia M. Müller , Wolfgang J. Paul (auth.) , Mikhail Kovalev

Book information

Publisher
Springer International Publishing
Year
2014
ISBN
978-3-319-13905-0, 978-3-319-13906-7
DOI
10.1007/978-3-319-13906-7
Language
english
Format
PDF
Filesize
5 MB (5751850 bytes)
Series
Lecture Notes in Computer Science 9000 Theoretical Computer Science and General Issues
Edition
1
Pages
352\359
Time added
2015-02-17 02:00:00
Algorithm Analysis and Problem Complexity; SoftwarCompilersInterpreters

Description

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

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