Applied Reconfigurable Computing: 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings

Description

This book constitutes the proceedings of the 15th International Symposium on Applied Reconfigurable Computing, ARC 2019, held in Darmstadt, Germany, in April 2019. The 20 full papers and 7 short papers presented in this volume were carefully reviewed and selected from 52 submissions. In addition, the volume contains 1 invited paper. The papers were organized in topical sections named: Applications; partial reconfiguration and security; image/video processing; high-level synthesis; CGRAs and vector processing; architectures; design frameworks and methodology; convolutional neural networks. Front Matter ....Pages i-xiii Front Matter ....Pages 1-1 Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging (Helena Cruz, Rui Policarpo Duarte, Horácio Neto)....Pages 3-16 Optimizing CNN-Based Hyperspectral Image Classification on FPGAs (Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk)....Pages 17-31 Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow (Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars)....Pages 32-47 A Novel Encoder for TDCs (Günter Knittel)....Pages 48-57 A Resource Reduced Application-Specific FPGA Switch (Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida)....Pages 58-67 Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications (Panagiotis G. Mousouliotis, Loukas P. Petrou)....Pages 68-77 Front Matter ....Pages 79-79 Probabilistic Performance Modelling when Using Partial Reconfiguration to Accelerate Streaming Applications with Non-deterministic Task Scheduling (Bruno da Silva, An Braeken, Abdellah Touhafi)....Pages 81-95 Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems (Tobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp, Jürgen Becker)....Pages 96-111 (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs (Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler)....Pages 112-126 Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan (Qazi Arbab Ahmed, Tobias Wiersema, Marco Platzner)....Pages 127-136 Secure Local Configuration of Intellectual Property Without a Trusted Third Party (Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche, Jürgen Becker)....Pages 137-146 Front Matter ....Pages 147-147 HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing (Lester Kalms, Ariel Podlubne, Diana Göhringer)....Pages 149-164 Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video Stream (Piotr Ciarach, Marcin Kowalczyk, Dominika Przewlocka, Tomasz Kryjak)....Pages 165-180 A Scalable FPGA-Based Architecture for Depth Estimation in SLAM (Konstantinos Boikos, Christos-Savvas Bouganis)....Pages 181-196 Front Matter ....Pages 197-197 Evaluating LULESH Kernels on OpenCL FPGA (Zheming Jin, Hal Finkel)....Pages 199-213 The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems (Jens Korinth, Jaco Hofmann, Carsten Heinz, Andreas Koch)....Pages 214-229 Graph-Based Code Restructuring Targeting HLS for FPGAs (Afonso Canas Ferreira, João M. P. Cardoso)....Pages 230-244 Front Matter ....Pages 245-245 UltraSynth: Integration of a CGRA into a Control Engineering Environment (Dennis Wolf, Tajas Ruschke, Christian Hochberger, Andreas Engel, Andreas Koch)....Pages 247-261 Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories (João Paulo C. de Lima, Paulo C. Santos, Rafael F. de Moura, Marco A. Z. Alves, Antonio C. S. Beck, Luigi Carro)....Pages 262-276 Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms (André Werner, Florian Fricke, Keyvan Shahin, Florian Werner, Michael Hübner)....Pages 277-291 Front Matter ....Pages 293-293 ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures (Ludovica Bozzoli, Luca Sterpone)....Pages 295-304 Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators (Johanna Rohde, Lukas Johannes Jung, Christian Hochberger)....Pages 305-316 Front Matter ....Pages 317-317 Hybrid Prototyping for Manycore Design and Validation (Leonard Masing, Fabian Lesniak, Jürgen Becker)....Pages 319-333 Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks (Umar Ibrahim Minhas, Roger Woods, Georgios Karakonstantis)....Pages 334-349 Front Matter ....Pages 351-351 Third Party CAD Tools for FPGA Design—A Survey of the Current Landscape (Brent E. Nelson)....Pages 353-367 Front Matter ....Pages 369-369 Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation (Masayuki Shimoda, Youki Sada, Hiroki Nakahara)....Pages 371-386 Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs (Ana Gonçalves, Tiago Peres, Mário Véstias)....Pages 387-401 Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning (Tiago Peres, Ana Gonçalves, Mário Véstias)....Pages 402-416 Back Matter ....Pages 417-418