A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide

Description

Now in a thoroughly revised second edition, this practical practitioner guide provides a comprehensive overview of the SoC design process. It explains end-to-end system on chip (SoC) design processes and includes updated coverage of design methodology, the design environment, EDA tool flow, design decisions, choice of design intellectual property (IP) cores, sign-off procedures, and design infrastructure requirements. The second edition provides new information on SOC trends and updated design cases. Coverage also includes critical advanced guidance on the latest UPF-based low power design flow, challenges of deep submicron technologies, and 3D design fundamentals, which will prepare the readers for the challenges of working at the nanotechnology scale. A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide, Second Edition provides engineers who aspire to become VLSI designers with all the necessary information and details of EDA tools. It will be a valuable professional reference for those working on VLSI design and verification portfolios in complex SoC designs Foreword to the First Edition by Faraj Aalaei Foreword to the First Edition by Ashok Soota Foreword to the First Edition by Walden C. Rhines Preface to the Second Edition Praise for the First Edition Preface to the First Edition About the Book Why read this book? What Problems Does It Solve? Who is the audience? What are the prerequisites to reading this book? Why become a VLSI designer? Contents Abbreviations Chapter 1: Introduction 1.1 Introduction to CMOS VLSI 1.2 Application Areas of SoC 1.3 Trends in VLSI 1.4 System on Chip Complexity 1.5 Integration Trend from Circuit to System on Chip 1.6 Speed of Operation 1.7 Die Size 1.8 Design Methodology 1.9 SoC Design and Development 1.10 Skill Set Required 1.11 EDA Environment 1.12 Challenges in All Reference Chapter 2: System on Chip (SoC) Design 2.1 Part 1 2.1.1 System on Chip (SoC) 2.2 Constituents of SoC 2.2.1 Processor Subsystem Cores 2.3 Application-Specific Processors 2.4 Control Processors 2.5 Digital Signal Processors 2.6 Vector Processors 2.6.1 Embedded Memory Core 2.6.2 Analog Cores 2.6.3 Interface Cores 2.6.4 On-Chip Clock Generators, PLLs, and Sensors 2.7 Part 2 2.7.1 SoC Development Life Cycle 2.8 SoC Design Requirements 2.9 Design Strategy 2.10 SoC Design Planning 2.11 System Modeling 2.12 System Module Development Feasibility Study 2.13 IP Design Decisions 2.14 Verification IPs 2.15 Target Technology Decision 2.16 Development Plan 2.17 EDA Tool Plan 2.18 Design Center Infrastructure 2.19 Computational Servers 2.20 Filers 2.21 Workstations 2.22 Backup Servers 2.23 Source Control Server 2.24 Firewalls 2.25 Resource Planning 2.26 SoC Design Flow 2.26.1 SoC Chip High-Level Design Methodology 2.26.2 Digital SoC Core Development Flow 2.26.3 Processor Subsystem Core Design 2.26.4 SoC Integrated Design Flow 2.27 EVM Design Development Flow 2.28 Software Development Flow 2.29 Product Integration Flow Chapter 3: SoC Constituents 3.1 SoC Constituents 3.1.1 Embedded Processor Subsystem for System on Chip Choice of Embedded Processors for SoC Embedded General-Purpose RISC Processors 3.1.2 DSP Processors 3.2 Issues of Hw-Sw Co-Design 3.2.1 Processor Subsystems 3.2.2 Processor Configuration Tools 3.2.3 Processor Development Boards 3.3 Embedded Memories 3.3.1 Types of Memories 3.3.2 Choice of Memories 3.3.3 Memory Compiler and Compiled Memories 3.4 Protocol Blocks 3.5 Mixed Signal Blocks 3.6 Radio Frequency (RF) Control Blocks 3.7 Analog Blocks 3.8 Third-Party IP Cores 3.9 System Software 3.9.1 OSI System Model Physical Layer (Layer 1) Data Link Layer (Layer 2) Network Layer (Layer 3) Transport Layer (Layer 4) Session Layer (Layer 5) Presentation Layer (Layer 6) Application Layer (Layer 7) 3.10 GAMP Classification of Software 3.10.1 Hardware 3.10.2 Device Driver 3.10.3 Firmware 3.10.4 Middleware 3.10.5 Software 3.10.6 Cloud 3.11 Design-Specific Blocks Chapter 4: VLSI Logic Design and HDL 4.1 SoC Design Concepts 4.1.1 Logic Design Fundamentals 4.1.2 System Clock and Clock Domains 4.1.3 Asynchronous and Synchronous Resets Metastability Standard Cells and Compiled Logic Blocks Hard and Soft Macros Data Buffers and Buffer Managers Design Assertions 4.1.4 Synchronous Sequential Functional Blocks 4.2 Asynchronous Circuits 4.3 Speed Matching 4.4 Network on Chip Architecture 4.5 Hardware Accelerator 4.6 Hardware Description Languages (HDL) 4.7 Behavioral Modelling of the Hardware System 4.8 Dataflow Modeling of the Hardware System 4.9 Structural Modeling of the Hardware System 4.10 Input-Output Pad Instantiation 4.10.1 Power Ground Corner Pad Instantiation (Fig. 4.17) Chapter 5: Synthesis and Static Timing Analysis (STA) 5.1 Part 1: SoC Synthesis 5.1.1 Set Synthesis Environment Read Library Read HDL Design Files Elaborate the Design Files Read Design Constraints Optimization Constraint Synthesis Analyze Generate Reports 5.1.2 SoC Design Constraints 5.2 Design Rule Constraints 5.3 SoC Design Synthesis 5.4 Low-Power Synthesis 5.4.1 Introduction to Low-Power SoCs 5.4.2 Universal Power Format (UPF) 5.5 Reports 5.5.1 Gate Level Netlist Verification 5.6 Part 2: Static Timing Analysis (STA) 5.7 Timing Definition 5.8 Timing Delay Calculation Concepts 5.9 Timing Analysis 5.10 Modeling Process, Voltage, and Temperature Variations 5.10.1 Equivalent Cells 5.11 Timing and Design Constraints 5.12 Organizing Paths to Groups 5.13 Design Corners 5.14 Challenges of STA During SoC Design Chapter 6: SoC Design for Testability (DFT) 6.1 Need for Testability 6.2 Guidelines for SoC Design for Testability 6.3 DFT Logic Insertion Techniques 6.3.1 Scan Insertion 6.3.2 Boundary Scan 6.4 Boundary Scan Insertion Flow 6.4.1 Memory Built-in Self-Test (MBIST) 6.4.2 Stuck-at Faults 6.4.3 Transition Faults 6.4.4 Coupling Faults 6.4.5 Neighborhood Pattern-Sensitive Faults 6.4.6 MBIST Algorithms 6.5 ROM Test Algorithm 6.6 Power Aware Test Module (PATM) Insertion 6.6.1 Logic BIST Insertion 6.6.2 Writing out DFT SDC 6.6.3 Compression Insertion 6.7 On-SoC Clock Generation (OSCG) Insertion 6.8 Challenges in SoC DFT 6.9 Memory Clustering 6.10 DFT Simulations 6.11 ATPG Pattern Generation 6.12 Automatic Test Equipment Testing (ATE Testing) Chapter 7: SoC Design Verification 7.1 Importance of Verification 7.2 Verification Plan and Strategies 7.3 Verification Plan 7.4 Functional Verification 7.5 Verification Methods 7.5.1 Black Box Verification 7.5.2 White Box Verification 7.5.3 Gray Box Verification 7.6 Design for Verification 7.7 Verification Example 7.8 Verification Tools 7.9 Verification Language 7.10 Automation Scripts 7.11 Design for Verification 7.12 Assertions in Verification 7.13 Verification Reuse and Verification IPs 7.14 Universal Verification Methodology (UVM) 7.15 Bug and Debug 7.16 Bug Tracking Workflow 7.17 Formal Verification 7.18 FPGA Validation 7.19 Validation on Development Boards Chapter 8: SoC Physical Design 8.1 Re-convergent Model of VLSI SoC Design 8.2 File Formats 8.3 SoC Physical Design 8.4 Physical Design Theory 8.5 Stick Diagrams 8.6 Physical Design Setup and Floor Plan 8.7 Floor Planning 8.8 SoC Power Plan 8.9 Two-Step Synthesis of SoC Design 8.10 Placement 8.11 Physical Design Constraints 8.12 Clock Tree Synthesis (CTS) 8.13 Routing 8.14 ECO Implementation 8.15 Advanced Physical Design of SOCs 8.15.1 For Low-Power Consumption 8.15.2 For Advanced Technology 8.15.3 High Performance 8.16 Photolithography and Mask Pattern Chapter 9: SoC Physical Design Verification 9.1 SoC Design Verification by Formal Verification 9.2 Model Checking 9.3 Logic Equivalence Check (LEC) 9.4 Static Timing Analysis (STA) 9.5 ECO Checks 9.6 Electromigration (EM) 9.7 Simultaneous Switching Noise (SSN) 9.8 Electrostatic Discharge (ESD) Protection 9.9 IR and Cross Talk Analysis 9.10 Layout Verse Schematic (LVS) 9.11 Gate Level Simulation 9.12 Electrical Rule Check (ERC) 9.13 DRC Rule Check 9.14 Design Rule Violation (DRV) Checks 9.15 Design Tape Out Chapter 10: SoC Packaging 10.1 Introduction to VLSI SoC Packaging 10.2 Classification of Packages 10.3 Criteria for Selection of Packages 10.4 Package Components 10.5 Package Assembly Flow 10.6 Packaging Technology 10.7 Flip-Chip Packages 10.8 Typical Packages 10.9 Package Performance 10.10 System Integration 10.11 Packaging Trends 10.11.1 Stacked Die Integration 10.11.2 3D Integration Schemes Chapter 11: Reference Designs 11.1 Design for Trial 11.2 Prerequisites 11.3 User Guidelines 11.4 Design Directory 11.5 Part 1 11.6 Design Examples 11.7 Part II 11.7.1 Design Flow 11.7.2 Logic Equivalence Check (LEC) 11.8 Part III 11.8.1 MINI-SoC Design IO Diagram Index