Inside an Open-Source Processor: An Introduction to RISC-V

Description

RISC-V is an Instruction Set Architecture (ISA) that is both free and open. This means that the RISC-V ISA itself does not require a licensing fee, although individual implementations may do so. The RISC-V ISA is curated by a non-profit foundation with no commercial interest in products or services that use it, and it is possible for anyone to submit contributions to the RISC-V specifications. The RISC-V ISA is suitable for applications ranging from embedded microcontrollers to supercomputers. This book will first describe the 32-bit RISC-V ISA, including both the base instruction set as well as the majority of the currently-defined extensions. The book will then describe, in detail, an open-source implementation of the ISA that is intended for embedded control applications. This implementation includes the base instruction set as well as a number of standard extensions. After the description of the CPU design is complete the design is expanded to include memory and some simple I/O. The resulting microcontroller will then be implemented in an affordable FPGA development board (available from Elektor) along with a simple software application so that the reader can investigate the finished design. Inside an Open-Source Processor Search... All rights reserved Dedicated to ... Table of Contents 1 • Introduction 1.1 Goals of This Book 1.2 Target Audience 1.3 Typeface Conventions 1.4 What to Expect 2 • RISC-V Instruction Set Architecture 2.1 Overview 2.2 Base Integer Instruction Set 2.3 Control and Status Register Extension 2.4 Integer Multiplication and Division Extension 2.5 Atomic Instruction Extension 2.6 Single-Precision Floating-Point Extension 2.7 Double-Precision Floating-Point Extension 2.8 Quad-Precision Floating-Point Extension 2.9 Compressed (16-bit opcode) Extension 2.10 Bit Manipulation Extension 2.11 External Debug Support 3 • Privileged Architecture 3.1 Privilege Levels 3.2 Control and Status Registers 3.3 Physical Memory Attributes 3.4 Physical Memory Protection 3.5 Supervisor Address Translation 3.6 Hypervisor Extension 3.7 Privileged Instructions 3.8 User-Level Interrupts Extension 4 • Initial Design Work 4.1 External Bus Interface 4.2 Instruction Timing 4.3 Load from Memory Timing 4.4 Store to Memory Timing 4.5 Atomic Memory Operation Timing 4.6 CSR Interface and Timing 4.7 Wait for Interrupt Timing 4.8 Breakpoint Timing 4.9 Reset Timing 5 • Organizing the Design 5.1 Verilog Coding Standards 5.2 Logic Synthesis Options 5.3 Instruction Decode Macro Definitions 5.4 Standard CSR Address Definitions 5.5 Exception Code Definitions 5.6 Top-level Module Connections 6 • Inside the CPU 6.1 Start-up and Pipeline Control 6.2 Stage 1: Memory Address Generation 6.3 Load/Store/AMO Logic 6.4 Stage 2: Memory Access 6.5 Stage 3: Pre-Decode 6.6 Stage 4: Register Read and Late Decode 6.7 Stage 5: Execute 6.8 CSR Interface 6.9 Stage 6: Register Write 7 • Inside the Control and Status Registers 7.1 Valid Address Check 7.2 Control/Status Registers 7.3 Debug Control/Status Registers 7.4 CSR Read Data 7.5 Cycle Counter 7.6 Instructions-Retired Counter 8 • Inside the Interrupts 8.1 Interrupt-Pending 8.2 Interrupt Outputs 8.3 Local Interrupts 9 • Hardware-Specific Modules 9.1 Register File Module 9.2 Adder Module 9.3 Subtractor Module 9.4 Incrementer Module 9.5 Counter Module 10 • Putting Everything Together 11 • Design Verification Testbench 11.1 Timing Generator 11.2 Processor Memory 11.3 Wait State Generation 11.4 Instantiate the Design 11.5 Error Log 11.6 End-of-Pattern Detect 11.7 Test Tasks 11.8 Test Patterns 12 • A RISC-V Microcontroller 12.1 Microcontroller Overview 12.2 Memory Module 12.3 Serial Port 13 • Alchrity FPGA Development System 13.1 FPGA Development Boards 13.2 Element Boards 13.3 Bank Signal Assignments 14 • Example FPGA Implementation 14.1 Example Hardware 14.2 Example Software 14.3 Memory Initialization 14.4 FPGA Project Setup 14.5 FPGA Results 14.6 Hardware Programming 15 • What Now? 15.1 Hardware Projects 15.2 Software Projects Appendix A • Resources Official RISC-V Alchrity FPGA Development RISC-V Programming YRV Verilog Code Index