Birthing The Computer: From Relays To Vacuum Tubes

Description

Birthing the Computer: From Relays to Vacuum Tubes is the first in a multi-volume series on historical computing machines. This series will span the development of computer systems from the Zuse machines of the early 1930s to about 1995 when microprocessors began to be commoditized. Each volume will focus on a range of technologies, or a class of machines or a particular vendor, and will describe the hardware of the machines and its peripherals, the operating system and system software, and its influence upon programming languages. This volume begins with the Zuse machines which were constructed from relays, but contained the basic elements of a computer system, namely input, computing engine, and output. Early machines from Atanasoff and Berry, Aiken, Stibitz, and IBM are described. The transition from relays to vacuum tubes increased speed and performance significantly, and led to the first true computers in ENIAC, EDSAC, and EDVAC which used paper tape and Williams tubes for I/O and storage. These machines were built by universities.Several early machines were purpose built such as Colossus and BINAC, and created with government support and industrial know-how. By the mid-to-late ‘50s, computing machines were being built by universities (the SSEM, Whirlwind, and IAS machines), governments (the NBS SEAC and SWAC, and several other machines), and industry (the UNIVAC series and the English Electric DEUCE). Most of these machines were constructed using the von Neumann architecture, and represent an evolution of thinking in how computing machines were to operate along with some innovative ideas in software and programming languages. By the end of the 1950s, the design, development, programming and use of computing machines were in full ferment as many new ideas were proposed, many different machines were designed and some were constructed. Computing machines became a commercial enterprise. Governments receded from building machines to levying requirements and funding construction, while universities continued to explore new architectures, new operating systems, and new programming languages. Table of Contents......Page 8 List of Figures......Page 17 List of Tables......Page 20 Acknowledgement......Page 24 Introduction......Page 25 Part I: Magnetic Drum Machines......Page 26 Chapter One......Page 28 1.1 650 System Architecture......Page 29 1.1.1 Magnetic Drum Memory......Page 30 1.1.2 Arithmetic Unit......Page 32 1.1.3 IBM 650 Self-Checking......Page 33 1.1.4 IBM 650 Console......Page 35 1.1.7 IBM 653 High-Speed Core Storage Unit......Page 36 1.2 IBM 650 Instruction Set......Page 37 1.2.2 Arithmetic Instructions......Page 38 1.2.4 Branching Instructions......Page 40 1.2.6 Miscellaneous Instructions......Page 41 1.2.8 Index Accumulator Operations Instructions......Page 42 1.2.9 Floating Point Instructions......Page 43 1.2.10 IAS Instruction......Page 44 1.3 IBM 650 Programming......Page 45 1.4 Symbolic Assembly......Page 46 1.5 IBM 650 RAMAC......Page 47 1.6 IBM 650 Assessment......Page 48 Chapter Two......Page 50 2.1 LGP-30 System Architecture......Page 52 2.2 LGP-30 Instruction Set......Page 53 2.3 The Story of Mel......Page 55 2.5 The LGP-21......Page 59 2.5.1 LGP-21 System......Page 60 2.5.2 LGP-21 Memory......Page 61 2.5.3 LGP-21 Control Registers......Page 62 2.6 LGP-21 Instruction Set......Page 64 2.8 LGP-21 Assessment......Page 66 3.1 Bendix G-15......Page 69 3.2 G-15 System Configuration......Page 75 3.2.2 Registers......Page 76 3.2.4 I/O System......Page 77 3.3 G-15 Instruction Set......Page 78 3.3.2 Special Instructions......Page 79 3.4.1 Magnetic Tape MTA-2......Page 81 3.4.4 Punched Card Coupler CA-1/CA-2......Page 82 3.5.1 ALGO......Page 83 3.5.2 Intercom 1000......Page 86 3.5.3 Sample G-15 Program......Page 91 3.6 Tracking Station Application......Page 92 3.7 G-15 Assessment......Page 93 Further Reading......Page 94 Exercises for the Reader......Page 95 Part II: Core Memory Machines......Page 98 Chapter Four......Page 102 4.1 BIZMAC System Architecture......Page 106 4.2 BIZMAC I/O System......Page 108 4.4 BIZMAC Instruction Set......Page 109 4.5 BIZMAC Assessment......Page 110 Chapter Five......Page 111 5.1.1 Central Processor......Page 114 5.1.2 Program Control......Page 115 5.1.3 Storage Hierarchy......Page 116 5.1.4 Virtual Storage......Page 117 5.3 Atlas Instruction Set......Page 119 5.3.1 Floating Point Arithmetic Instructions......Page 121 5.3.2 Indexing Operations......Page 122 5.3.3 Atlas Branching Instructions......Page 123 5.3.5 Atlas Odd/Even test Instructions......Page 124 5.3.7 Atlas Instruction Example......Page 125 5.4 Atlas Programming......Page 126 5.5 The Atlas Supervisor......Page 127 5.5.1 Structure of the Atlas Supervisor......Page 128 5.5.2 Job Structure......Page 130 5.5.4 Process Control......Page 131 5.5.5 Interrupt Handling......Page 132 5.6 Atlas 2......Page 133 5.6.1 Atlas 2 Central Processor......Page 134 5.6.2 Atlas 2 Memory......Page 135 5.6.3 Magnetic Tape......Page 137 5.7 The Atlas 2 Supervisor......Page 138 5.7.1 Interrupt Routines......Page 139 5.7.2 Supervisor Extracode Routines......Page 140 5.7.4 Object Programs......Page 141 5.8 Atlas Assessment......Page 142 Chapter Six......Page 145 6.1 JOHNNIAC System Architecture......Page 147 6.2 JOHNNIAC System Configuration......Page 148 6.3.1 Conditional Transfer Orders......Page 149 6.3.2 Transfer Orders......Page 150 6.3.3 Add Orders......Page 151 6.3.4 Multiply Operations......Page 152 6.3.5 Division Orders......Page 154 6.3.7 Register Movement Orders......Page 155 6.3.8 Shift Orders......Page 156 6.3.9 Input/Output Orders......Page 157 6.3.10 Drum Orders......Page 158 6.3.12 Control Orders......Page 159 6.4 JOHNNIAC Operation......Page 160 6.5 JOSS......Page 161 6.5.1 JOSS Structure......Page 162 6.5.2 JOSS Remote Console......Page 163 6.5.3 JOSS Implementation......Page 164 6.6 JOHNNIAC Assessment......Page 165 Further Reading......Page 166 Exercises for the Reader......Page 168 Part III: Transistor Machines......Page 170 Chapter Seven......Page 172 7.1 Solid State Computer Architecture......Page 173 7.1.1 SSC Central Processor......Page 177 7.1.2 Magnetic Drum......Page 178 7.1.3 Operator’s Console......Page 179 7.2 SSC80/SSC90 Instructions......Page 180 7.2.3 Transfer Instructions......Page 181 7.2.5 Comparison Instructions......Page 182 7.2.8 Card Reader Control Instructions......Page 183 7.3 SSC Peripherals......Page 184 7.4.1 FLOW-MATIC......Page 185 7.5 SSC Assessment......Page 186 Chapter Eight......Page 187 8.3 Instruction Format......Page 188 8.3.2 Type II Instructions......Page 189 8.5 UNIVAC 418-II......Page 190 8.6 UNIVAC 418-III......Page 191 8.6.1 UNIVAC 418-III System Architecture......Page 192 8.6.2 Command/Arithmetic Unit (CAU)......Page 193 8.6.3 Main Storage......Page 194 8.6.4 I/O Modules (IOMs)......Page 195 8.6.5 Magnetic Drums......Page 198 8.6.7 Communications Systems......Page 199 8.7 UNIVAC 418 System Software......Page 200 8.7.1 RTOS Executive......Page 201 8.7.2 Programming Languages......Page 206 8.7.3 System Applications......Page 207 8.8 UNIVAC 418 Assessment......Page 208 Chapter Nine......Page 210 9.1 UNIVAC 494......Page 212 9.1 System Architecture......Page 213 9.1.1 Central Processor......Page 214 9.1.3 I/O System......Page 216 9.1.4 Communications Handling......Page 218 9.1.5 Transfer Switch......Page 219 9.2 Instruction Set......Page 220 9.2.1 Shift Instructions......Page 222 9.2.2 UNIVAC 494 Transfer Instructions......Page 224 9.2.3 Arithmetic Instructions......Page 226 9.2.4 Logical Instructions......Page 228 9.2.5 Comparison Instructions......Page 229 9.2.6 Jump Instructions......Page 230 9.2.7 Sequence Modifying Instructions......Page 231 9.2.8 I/O Instructions......Page 232 9.3 Peripherals......Page 233 9.3.1 Magnetic Drums......Page 234 9.3.4 High-Speed Printer Subsystem......Page 235 9.4.2 Input Cooperative......Page 236 9.5 UNIVAC 490/494 Assessment......Page 237 Chapter Ten......Page 239 10.1.1 TX-0 Registers......Page 242 10.2 TX-0 Instructions......Page 243 10.2.1 TX-0 Operate Instructions......Page 244 10.2.2 Combining Instructions......Page 245 10.2.3 Modified Instruction Set......Page 247 10.3 Operating Modes......Page 248 10.5 FLIT......Page 249 10.7 TX-2......Page 250 10.7.1 TX-2 System Architecture......Page 251 10.8 TX-0 and TX-2 Assessment......Page 252 Chapter Eleven......Page 254 11.1 Philco 1000......Page 255 11.1.1 Philco 1000 Central Processor......Page 256 11.1.3 Instruction Set......Page 257 11.2 Philco TRANSAC S-2000......Page 258 11.3 TRANSAC S-2000 System Architecture......Page 263 11.3.1 Secondary Memory......Page 264 11.4 TRANSAC S-2000 Instruction Set......Page 265 11.4.3 Algorithm Control......Page 266 11.5 Philco 212......Page 267 11.5.2 Instruction Unit......Page 270 11.5.3 Index Unit......Page 271 11.5.4 Arithmetic Unit......Page 272 11.5.6 I/O Subsystem......Page 273 11.5.7 Real-Time System......Page 274 11.5.8 Philco 212 Instruction Set......Page 275 11.6 Operating System 32KSYS......Page 290 11.7 TRANSAC S-2000 Software......Page 291 11.8 Philco 2400 Input/Output System......Page 294 11.8.1 Philco 2400 System Architecture......Page 295 11.8.2 Executive Control......Page 296 11.8.3 Program Control......Page 297 11.8.5 Main Memory......Page 298 11.8.6 Operator Control Panel......Page 299 11.8.8 I/O Operations......Page 300 11.8.9 Internal Operations......Page 304 11.8.10 Arithmetic Operations......Page 309 11.9 Assessment of the Philco Machines......Page 312 12.1 Bendix G-20 System Architecture......Page 314 12.1.2 Registers......Page 317 12.1.4 Interrupts......Page 318 12.2.1 Add/Subtract Operations and Tests......Page 319 12.2.2 Logic Operations and Tests......Page 321 12.2.3 Repeated Commands......Page 322 12.2.5 Storage Operations......Page 323 12.2.7 Control Operations......Page 324 12.2.8 I/O Operations......Page 325 12.2.9 Bus Register Operations......Page 326 12.4 G-21 Dual Processor......Page 327 12.5 Bendix G-20 Assessment......Page 328 Chapter Thirteen......Page 329 13.1 PB250 System Architecture......Page 331 13.1.1 Central Processor......Page 332 13.1.2 Main Memory......Page 333 13.1.3 Flexowriter......Page 334 13.1.5 HYCOMP 250......Page 335 13.2 PB250 Commands......Page 336 13.2.1 Class I Commands......Page 337 13.2.2 Class II Commands......Page 339 13.2.4 Class IV Commands......Page 341 13.2.5 Sequence Tag......Page 342 13.3 Packard Bell 440......Page 343 13.3.1 PB440 System Architecture......Page 346 13.3.2 Memory System......Page 347 13.3.3 I/O System......Page 348 13.3.4 PB440 Programming......Page 349 13.5 Packard Bell Assessment......Page 350 Further Reading......Page 352 Exercises for the Reader......Page 353 Appendix A: Glossary......Page 356 References......Page 357 Index......Page 365