An Introduction to Microcomputers: Some Real Microprocessors

Description

This is the third part (yes, third) of a series of books covering early microprocessor technology. Originally written in the 70s and not recently repubished, this series of books appears to be stuck-fast within the time and scope of its writing. Covering a wide range of period-specific and lasting topics and design theory, it gives a nice perspective into the technology that preceded and shaped what we use today. Many of the most used chips of the time are still produced in the modern era for legacy repair, compatibility, and cost reduction. So is it still worth a read? I think so. - Super Secret Uploadie Person, 2022 The whole series of "An Introduction to Microcomputers": Volume 0 — The Beginner's Book ISBN 0931988640 Volume 1 — Basic Concepts, second edition ISBN 0931988020 Volume 2 — Some Real Microprocessors ISBN 0931988152 Volume 3 — Some Real Support Devices ISBN 0931988187 4-Bit Microprocessors and the TMS1000 Series Microcomputers 1-1 Q TMS1000 Programmable Registers 1-3 ~ TMS1000 Memory Addressing Mode 1-5 a: Q. TMS1000 Status Flags 1-5 a: TMS1000 Input and Output Logic 1-5 0 CJ TMS1000 Series Microcomputer Pins and Signals 1-6 ~ TMS 1000 Series Microcomputer Instruction Execution 1-10 w TMS 1000 Series Microcomputer Instruction Set 1-10 ~ The Benchmark Program 1-10 U Data Sheets 1-01 The Mostek 3870 (and Fairchild F8) CI) 2 2-1 ~ The 3870 One-Chip Microcomputer 2-3 w 3870/F8 Programmable Registers 2-5 a: 3870 Memory Addressing Modes 2-6 0 In 3870/F8 Status Flags 2-9 CI) 3870 Pins and Signals 2-9 3870 Instruction Timing and Execution 2-11 ~ 3870 I/O Ports 2-11 ~ 3870 Interrupt Logic 2-13 @ Timer/Counter Logic 2-15 The 3870 Control Code 2-17 The 3870/F8 Instruction Set 2-19 The 3870 Benchmark Program 2-26 The 3850 CPU 2-29 F8 Programmable Registers and Status Flags 2-31 F8 Addressing Modes 2-31 F8 Clock Circuits 2-32 F8 CPU Pins and Signals 2-34 F8 Timing and Instruction Execution 2-35 F8 I/O Ports 2-37 A Summary of F8 Interrupt Processing 2-37 The F8 Instruction Set 2-37 The Benchmark Program 2-38 The 3851 Program Storage Unit (PSU) 2-39 The 3851 PSU Read-Only Memory 2-40 3851 PSU Input/Output Logic 2-41 3851 PSU Interrupt Logic 2-42 3851 PSU Programmable Timer Logic 2-45 3851 PSU Data Transfer Timing 2-45 Using the 3851 PSU in Non-F8 Configurations 2-45 The 3861 and 3871 Parallel I/O (PIO) Devices 2-47 The 3856 and 3857 16K Programmable Storage Units (16K PSU) 2-47 Additional F8 Support Devices 2-49 The 3852 Dynamic Memory Interface (DMil 2-49 The 3854 Direct Memory Access (DMA) Device 2-53 The 3853 Static Memory Interface (SMil 2-54 Data Sheets 2-01 3 The National Semiconductor SC/MP 3-1 SCiMP Programmable Registers 3-3 Addressing Modes 3-4 SC/MP Status Register 3-5 SC/MP CPU Signals and Pin Assignments 3-5 SC/MP Timing and Instruction Execution SC/MP Bus ..;\ccess Logic SCiMP Input/Output Operations The SC/MP Halt State SC/MP Interrupt Processing SC/MP DMA and Multiprocessor Operations The SC/MP Reset Operation SCiMP Serial Input/Output Operations The SC/MP Instruction Set The Benchmark Program Support Devices for the SC/MP CPU Using Other Microcomputer Support Devices with the SC/MP CPU Data Sheets The8080A The SOSOA CPU SOSOA Programmable Registers SOSOA Addressing Modes SOSOA Status 8080A CPU Pins and Signals SOSOA Timing and Instruction Execution Clock Signals Instruction Fetch Sequence A Memory Read or Write Operation Separate Stack Memory Modules The Wait State The Wait. Hold and Halt States The Hold State The Halt State and Instruction The Reset Operation External Interrupts External Interrupts During the Halt State Wait and Hold Conditions Following an Interrupt The S080A Instruction Set . The Benchmark Program Instruction Execution Times and Codes Support Devices that may be Used with the SOSOA The 8224 Clock Generator and Driver The 8224 Clock Generator Pins and Signals The 8228 and 8238 System Controller and Bus Driver Bus Driver Logic Control Signal Logic 8228 System Controller Pins and Signals The 8259 Priority Interrupt Control Unit (PICU) 8259 PICU Pins and Signals The 8259 PICU Interrupt Acknowledge Vector 8259 PICU Priority Arbitration Options How Interrupt Requests and Priority Status are'Recorded Programming the 8259 PICU The TMS 5501 Multifunction Input/Output Controller TMS 5501 Device Pins and Signals TMS 5501 Device Access TMS 5501 Interrupt Handling TMS 5501 Parallel I/O Operations TMS 5501 Serial I/O Operation TMS 5501 Interval Timers Data Sheets The 8085 The 8085A CPU 8085A Programmable Registers 8085A Addressing Modes 8085A Status 8085A CPU Pins and Signals A Comparison of 8085A and 8080A Signals 8085A Timing and Instruction Execution· The Clock Signals Memqry Access Sequences Bus Idle Machine Cycles The Wait State The SID and SOD Signals The Hold State The Halt State and Instruction External Interrupts The Reset Operation The 8085A Instruction Set 8085A Microprocessor Support Devices The 8155/815.6 Static Read/Write Memory with 1/0 Ports and Timer 8155/8156 Device Pins and Signals 8155/8156 ParaliellnputlOutput 8155/8156 Device Addressing The 8155/8156 CounterlTimer 8155/8156 Control and Status Registers 8155/8156 Device Programming The 8355 Read-Only Memory with I/O 8355 Device Pins and Signals 8355 Ready Logic 8355110 Logic The 8755A Erasable Programmable Read-Only Memory with 1/0 Data Sheets The 8048 Microcomputer Devices The 8048. 8748. 8049.8749 and 8035 Microcomputers An 8048 and 8049 Functional Overview 8048. 8748. and 8035 Microcomputer Programmable Registers 8048 Series Addressing Modes A Program Memory Map 8048 Series Status 8048 Series Microcomputer Operating Modes 8048 Series Microcomputer Pins and Signals 8048 Series Timing and Instruction Execution Internal Execution Mode External Memory Access Mode Debug Mode Single Stepping Programming Mode Verification Mode InputlOutput Programming Hold State CounterlTimer Operations Internal and External Interrupts The 8048 Microcomputer Series Instruction Set The Benchmark Progra~ The 8041 Slave Microcomputer An 8041 Functional Overview 8041 Data Bus Logic 8041 I/O Ports One and Two 8041 and 8741 Programmable Registers 8041 and 8741 Addressing Modes 8041 and 8741 Status 8041 and 8741 Slave Microcomputer Operating Modes 8041 and 8741 Pins and Signals . 8041 Series Timing and Instruction Execution 8741 Single Stepping and Programming Mode 8041 Input/Output Programming 8041 CounterlTimer Operations 8041 Interrupt Logic Programming 8048-8041 Data Transfers The 8041/8741 Instruction Set The 8021 Single-Chip Microcomputer An 8021 Fu nctional Overview 8021 I/O Port Pins The T1 Pin The 8021 Reset Input The 8021 Clock Inputs The 8021 Timer/Counter 8021 Scratchpad Memory and Programming The 8243 Input/Output Expander 8243 Input/Output Expander Pins and Signals 8243 Input/Output Expander Operations Data Sheets ZilogZ80 The Z80 CPU A Summary of Z80/8080A Differences Z80 Programmable Registers Z80 Addressing Modes Z80 Status Z80 CPU Pins and Signals Z80-8080A Signal Compatibility Z80 Timing and Instruction Execution Instruction Fetch Execution Sequences A Memory Read Operation Memory Write Operation The Wait State Input or Output Generation Bus Requests External Interrupts The Halt Instruction The Z80 Instruction Set Input/Output Instructions Primary Memory Reference Instructions Block Transfer and Search Instructions Secondary Memory Reference (Memory Operate) Instructions Immediate Instructions Jump Instructions Subroutine Call and Return Instructions Immediate Operate Instructions Jump-on-Condition Instructions Register-Register Move Instructions Register-Register Operate Instructions Register Operate Instructions Bit Manipulation Instructions Stack Instructions I nterrupt Instructions Status and Miscellaneous Instructions The Benchmark Program Support Devices that may be Used with the Z80 The Z80 Parallel 110 Interface (PIO) Z80 PIO Pins and Signals Z80 PIO Operating Modes Z80 PIO Interrupt Servicing Programming the Z80 PIO The Z80 Clock Timer Circuit (CTC) Z80 CTC Functional Organization Z80 CTC Pins and Signals Z80 CTC Operating Modes Z80 CTC Interrupt Logic Programming the Z80 CTC Data Sheets The Motorola MC6800 The MC6800 CPU The MC6800 Programmable Registers MC6800 Memory Addressing Modes MC6800 Status Flags MC6800 CPU Pins and Signals MC6800 Timing and Instruction Execution The Hold State. the Halt State and Direct Memory Access Interrupt Processing. Reset and the Wait State The MC6800 Instruction Set The Benchmark Program MC6800 Summary of Cycle by Cycle Operation Support Devices that may be Used with the MC6800 The MC6802 CPU with Read/Write Memory The MC6870 Two Phase Clocks The MC6870A Clock Device The MC6871A Clock Device The MC6871 B Clock Device The MC6875 Clock Device Some Standard Clock Signal Interface Logic The MC6820 and MCS6520 Peripheral Interface Adapter (PIA) The MC6820 PIA Pins and Signals MC6820 Operations The MC6850 Asynchronous Communications Interface Adapter (ACIA) The MC6850 ACIA Pins and Signals MC6850 Data Transfer and Control Operations MC6850 ACIA Control Codes and Status Flags The MC6852 Synchronous Serial Data Adapter (SSDA) MC6852 SSDA Pins and Signals MC6852 Data Transfer and Control Operations MC6852 Status Register The MC6852 Control Registers Programming the MC6852 The MC8507 (or MC6828) Priority Interrupt Controller (PIC) MC6828 Pins and Signals The Interrupt Acknowledge Process I nterru pt Priorities Interrupt Inhibit Logic The MC6840 Programmable CounterlTimer The MC6840 CounterlTimer Pins and Signals MC6840 Addressing MC6840 CounterfTimer Programmable Options The MC6844 Direct Memory Access Controller MC6844 DMA Controller Pins and Signals MC6844 Addressable Registers MC6844 DMA Transfer Modes MC6844 DMAC Three7State Control. Cycle Stealing Mode MC6844 DMAC Halt Modes Comparing MC6844 DMAC Modes Using an MC6844 DMAC with Mixed Modes The MC6844 Control Registers and Operating Options Resetting the MC6844 DMAC Programming the MC6844 DMAC The MC6846 Multifunction Support Device MC6846 Multifunction Device Pins and Signals MC6846 CounterfTimer Logic MC6846 I/O Port Logic MC6846 Device Reset Data Sheets The MOS Technology MCS6500 The MCS6500 Series CPUs MCS6500 Series CPU Programmable Registers MCS6500 Memory Addressing Modes MCS6500 Status Flags MCS6500 CPU Pins and Signals MCS6500 Timing and Instruction Execution Interrupt Processing and System Reset MCS6500 CPU Clock Logic MCS6500 CPU Interface Logic The MCS6500 Instruction Set The Benchmark Program Support Devices that may be Used with the MCS6500 Series Microprocessors The MCS6522 Peripheral Interface Adapter MCS6522 PIA Pins and Signals MCS6522 Parallel Data Transfer Operations MCS6522 Interval Timer Logic MCS6522 Shifter Logic MCS6522 Interrupt Logic The MCS6530 Multifunction Support Logic Device MCS6530 Multifunction Device Pins and Signals MCS6530 Parallel Data Transfer Operations MCS6530 Interval Timer and Interrupt Logic The MCS6532 Multifunction Support Logic Device MCS6532 Multifunction Device Pins and Signals MCS6532 Logic Functions Data Sheets The signetics 2650A The 2650A CPU Logic 2650A Programmable Registers The 2650A Memory Addressing Modes The 2650A Status Flags The 2650A CPU Pins and Signals Interfacing Memory to the 2650A MicrocompLiter Interfacing I/O Devices to the 2650A Microcomputer The 2650A Microcomputer Instruction Process 2650A Microcomputer Direct Memory Access The 2650A Microcomputer Instruction Set The 2650A Benchmark Program Support Devices that may be Used with the 2650A Microprocessor Data Sheets . The RCA COS MAC The COSMAC CPU COS MAC Programmable Registers COSMAC Memory Addressing Modes COSMAC Status Flags COS MAC CPU Pins and Signals COSMAC Timing and Instruction Execution, COSMAC Memory Read Timing COSMAC Memory Write Instruction Timing COS MAC Data Input Data Output and Direct Memory Access A Summary of COSMAC Interrupt Processing The COSMAC Instruction Set The Benchmark Program Using COSMAC with Other Microprocessor Support Devices The CDP1852 Parallel I/O Port CDP1852 Pins and Signals CDP 1852 Operations Overview CDP1852 Input Operations CDP1852 Output Operations Data Sheets . IM6100 Microcomputer Devices The IM6100 CPU IM6100 Programmable Registers IM6100 Memory Space IM6100 Memory Addressing Modes IM61 00 Status Flags IM6100 CPU Pins and Signals IM61 00 Timing and Instruction Execution IM6100 No Operation Machine Cycle IM6100 Data Input Machine Cycle IM6100 Data Output Machine Cycle IM6100 Address Demultiplexing IM61 00 Memory Read Machine CycleTimirig IM6100 Memory Write Machine Cycle IM6100 Input/Output Timing IM61 00 Wait State IM6100 Hold and Halt Conditions IM6100 Direct Memory Access The IM6100 Reset IM61 00 Interrupt Logic IM6100 Control Panel Logic External Control Signal Priorities IM6100 Instruction Set The IM6100 Benchmark Program. Some SpeciallM6100 Hardware Considerations Implementing a Hardware Stack Support Devices that may be Used with the IM61 00 The IM6101 Parallel Interface Element (PIE) IM6101 Parallel Interface Element Pins and Signals IM6101 Functional Logic IM6101 Interrupt Handling Logic The IM6102 MEDIC IM6102 MEDIC Pins and Signals The IM6100-IM61021nterface IM6102 Extended Memory Control IM61 02 Extended Memory Programming Considerations IM6102 Extended Memory Interrupt Considerations IM6102 Dynamic Memory Refresh and Direct Memory Access Logic IM61 02 Programmable Real-Time Clock Logic IM61 02 MEDIC Instructions Data Sheets The 8X300 (or SMS300) The 8X300 Microcontroller 8X300 Addressable Registers 8X300 Status Flags 8X300 Memory Addressing 8X300 Pins and Signals 8X300 Instruction Execution and Timing The 8X300 Instruction Set The 8X300 Benchmark Program The 8T32. 8T33. 8T35. and 8T36 Interface Vector Byte (IV Byte) 8T32/3/5/6 IV Byte Pins and Signals 8T32/3/5/6 IV Byte Operation 8T32/3/5/6 IV Byte Addresses The 8T39 and 8T58 Bus Expanders Data Sheets The National Semiconductor PACE and INS8900 PACE and INS8900 Microcomputer System Overviews INS8900 Programmable Registers INS8900 Stack INS8900 and PACE Addressing Modes INS8900 and PACE Status and Control Flags INS8900 and PACE CPU Pins and Signals INS8900 and PACE Timing and Instruction Execution The Initialization Operation The Halt State and Processor Stall Operations Direct Memory Access Operations The INS8900 and PACE Interrupt System The INS8900 and PACE Instruction Set The Benchmark Program The PACE DP8302 System Timing Element (STE) The PACE Bidirectional Transceiver Element (BTE) 15-36 Using Other Microcomputer Support Devices with the PACE and INS8900 15-38 0 Data Sheets 15-01 w le:( 16 The General Instrument CP1600 16-1 a: 0 a.. The CP1600 Microcomputer System Overview 16-1 a: 0 CP1600 Programmable Registers 16-3 0 CP1600 Memory Addressing Mode 16-3 ~ u) CP1600 Status and Control Flags 16-6 w CP1600 CPU Pins and Signals 16-6 le:( CP1600 Instruction Timing and Execution 16-10 (; CP1600 Memory Access Timing 16-10 0 (I) The CP 1600 Wait State 16-12 (I) e:( The CP1600 Halt State 16-12 G/.I CP 1600 Initialization Sequence 16-13 w z CP1600 DMA Logic 16-13 a: 0 The CP1600 Interrupt Logic 16-15 III (I) The CP1600 Instruction Set 16-16 0 The Benchmark Program 16-25 ~ e:( Support Devices that may be Used with the CP1600 16-27 0 The CP1680 Input/Output Buffer (lOB) 16-30 e:( @ CP1680 lOB Pins and Signals 16-30 CP16BO Addressable Registers 16-31 The CP1680 Control Register 16-32 CP1680 Data Transfer Operations 16-33 The CP1680 Interval Timer 16-36 CP1680 Interrupt Logic 16-37 Data Sheets 16-01 17 The General Instrument 1650 Series Microcomputers 17-1 A 1650 Functional Overview 17-1 1650 Series Microcomputer Programmable Registers 17-4 1650 Series Microcomputer Memory Addressing Modes 17-6 1650 Series Microcomputer Pins and Signals 17-6 1650 Series Microcomputer Instruction Set 17-8 The 1650 Benchmark Program 17-9 Data Sheets 17-01 18 The Texas Instruments TMS 9900. TMS 9980, and TMS 9440 Products 18-1 The TMS 9900 Microprocessor 18-2 A TMS 9900 Functional Overview 18-2 TMS 9900 Programmable Registers 18-3 TMS 9900 Memory Addressing Modes 18-6 TMS 9900 I/O Addressing 18-8 TMS 9900 CPU Pins and Signals 18-13 TMS 9900 Timing and Instruction Execution 18~ 15 Memory Access Operations 18-15 Memory Select Logic 18-19 TMS 9900 I/O Instruction Timing 18-20 The Wait State 18-23 The Hold State 18-25 The Halt Stelte 18-25 TMS 9900 Interrupt Processing Logic 18-26 The TMS 9900 Reset 18-34 The TMS 9900 Load Operation The TMS 9900 Instruction Set The Benchmark Program The TMS 9980A and the TMS 9981 Microprocessors TMS 9980 Series Microprocessor Pins and Signals TMS 9980 Series Microprocessor Timing and Instruction Execution TMS 9980 Series Interrupt Logic The TMS 9980 Series Instruction Set The TMS 9940 Single-Chip Microcomputers TMS 9940 Registers and Read/Write Memory TMS 9940 CPU Pins and Signal Assignments TMS 9940 General Purpose Flags TMS 9940 Timer/Event Counter Logic TMS 9940 Interrupt Logic TMS 9940 Reset Programming a TMS 9940E Erasable Programmable Read-Only Memory Loading a Program into TMS 9940 Read/Write Memory The TMS 9940 Instruction Set The TIM 9904 Four-Phase Clock Generator/Driver The TMS 9901 Programmable System Interface (PSI) TMS 9901 Pins and Signals TMS 9901 PSI Interrupt Logic TMS 9901 Data Input and Output TMS 9901 Real-Time Clock Logic TMS 9901 Reset Logic Data Sheets Single Chip Nova Minicomputer Central Processing Units A Product Overview Nova Programmable Registers Nova Memory Addressing Modes Nova Status Flags MicroNova and 9440 CPU Pins and Signals CPU Logic and Instruction Execution. Arithmetic/Logic Instructions Memory Reference Instructions Input/Output Instructions A Nova Summary 9440 Timing and Instruction Execution MicroNova and 9440 Interrupt Processing MicroNova and 9440 Direct Memory Access Logic The MicroNova and 9440 Instruction Sets The Benchmark Program Data Sheets The Intel 8086 The 8086 CPU 8086 Programmable Registers and Addressing Modes 8086 Status 8086 CPU Pins and Signals 8086 Timing and Instruction Execution 8086 Bus Cycles 8086 Instruction Queue 8086 Memory and I/O Device Read Bus Cycle for Simple Configurations 8086 Memory or I/O Device Write Bus Cycle for Minimum Mode 8086 Read and Write Bus Cycles for Maximum Mode The 8086 Wait State 20-34 The 8086 Hold State 20-34 c The 8086 Halt State 20-36 w The 8086 Lock 20-37 ~ a: The 8086 Processor Wait for Test State 20-38 0 a. The 8086 Processor Escape 20-38 a: 0 The 8086 Reset Operation 20-38 CJ 8086 Interrupt Processing 20-38 ~ iii Single Stepping Mode 20-41 w The 8086 Instruction Set 20-41 ~ < 8086-8080A Instruction Compatibility 20-48 g The Benchmark Program 20-48 CI) CI) Instruction Execution Times and Codes 20-67 < The Intel 8284 Clock Generator/Driyer 20-77 o1J 8284 Clock Generator/Driver Pins and Signals 20-77 w z The Intel 8288 Bus Controller 20-80 a: 0 8288 Bus Controller Signals and Pin Assignments 20-80 III CI) The 8282/8283 8-Bit Input/Output Port 20-83 0 The 8282/8283 Input/Output Port Pins and Signal Assignments 20-83 ~ < The 8286/8287 8-Bit Bidirectional Bus Transceivers 20-85 c 8286 and 8287 Bidirectional Bus Transceiver Pins and Signal Assignments 20-85 < @ Some 8086 Microprocessor Bus Configurations 20-86 Data Sheets 20-D1 22 2900 Series and 6700 Series Chip Slice Products 22-1 The 2901/6701 Arithmetic and Logic Unit (ALU) 22-2 The 2909 Microprogram Sequencer 22-5 The 2902 Carry Look Ahead 22-8 Data Sheets 22-D1 23 The MC1 0800 Series Chip Slice Logic 23-1 The MC1 0800 Arithmetic and Logic Unit Slice 23-3 The MC 10801 Microprogram Control Unit 23-5 The MC1 0802 Timing Device 23-6 The MC1 0803 Memory Interface Device 23-6 Data Sheets 23-D1 24 The Hewlett Packard MC2 24-1 An MC2 System Overview 24-1 MC2 Programmable Registers and Status 24-2 MC2 Memory Addressing Modes 24-4 Hardware Aspects of the MC2 24-4 The MC2 Instruction Set 24-5 The Benchmark Program 24-6 25 Selecting a Microcomputer 25-1 Designing Logic with Microcomputers -A Sequence of Events 25-2 Microcomputer Development Hardware 25-3 Microcomputer System Software 25-5 An Economic Example 25-9 A Look at the Future 25-10