Digital Systems : Principles and Design (For Anna University)

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Cover Contents Preface Acknowledgements Chapter 1: Basic Digital Concepts 1.1 Concepts of ‘1’s, ‘0’s 1.1.1 Positive Logic 1.1.2 Negative Logic 1.1.3 Popular Representations of the Digital Circuits 1.2 Analog vs. Digital Circuits Chapter 2: Boolean Algebra and Theorems, Minterms and Maxterms 2.1 The NOT, AND, OR Logic Operations 2.1.1 The NOT Logic Operation 2.1.2 The AND Logic Operation 2.1.3 The OR Logic Operation 2.2 The NAND and NOR Logic Operations 2.2.1 NAND Gate 2.2.2 NOR Gate 2.3 The XOR, NOT-XOR, NOT-NOT Logic Operations 2.3.1 XOR Logic Operation 2.3.2 NOT-XOR (XNOR) Logic Operation 2.3.3 NOT-NOT Logic Operation 2.4 Boolean Algebraic Rules (for Outputs from the Inputs) 2.4.1 OR Rules 2.4.2 AND Rules 2.4.3 NOT Rules (Rules of Complementation) 2.5 Boolean Algebraic Laws 2.5.1 Commutative Laws 2.5.2 Associative Laws 2.5.3 Distributive Laws 2.6 Demorgan Theorems 2.7 The Sum of the Products (SOPs) as per Boolean Expression and Minterms 2.7.1 SOPs for Two Variables (Two Inputs) Case 2.7.2 SOPs for Three Variables (Three Inputs) Case 2.7.3 SOPs for Four Variables (Four Inputs) Case 2.7.4 Conversion of a Boolean Expression or Truth Table Outputs into the Standard SOP Format 2.8 Product of the Sums and Maxterms for a Boolean Expression 2.8.1 POS for Two Variables (Two Inputs) Case 2.8.2 POS for Three Variables (Three Inputs) Case 2.8.3 POS for Four Variables (Four Inputs) Case 2.8.4 Conversion of a Boolean Expression into Standard POS Format Chapter 3: Karnaugh Map and Minimization Procedures 3.1 The Three-Variable Karnaugh Map and Tables 3.1.1 Karnaugh Map from the Truth Table 3.1.2 Karnaugh Map from the Minterms in a SOP 3.1.3 Karnaugh Map from the Maxterms in a POS 3.2 Four Variable Karnaugh Map and Tables 3.2.1 Karnaugh Map from the Truth Table 3.2.2 Karnaugh Map from the Minterms in an SOP 3.2.3 Karnaugh Map from the Maxterms in a POS 3.3 Five and Six Variable Karnaugh Maps and Tables 3.4 An Important Feature in the Design of a Karnaugh Map 3.4.1 Only Single Variable Changes into Its Complement in a Pair of Adjacent Cells 3.4.2 Only Two Variables Change into Their Complements in Adjacent Cells in a Square or Column of Four Cells 3.4.3 Three Variables Change into Their Complements in Adjacent Cells in Box of Eight Adjacent Cells 3.4.4 First and Last Columns for First and Last Rows and Purpose of Deciding Adjacency in a Karnaugh Map 3.4.5 Use of Don’t Care (or Unspecified) Input Conditions for Purpose of Deciding Adjacencies in a Karnaugh Map 3.5 Simplification of Logic Circuit Relation by Minimization Using Adjacencies 3.5.1 Minimization of a Karnaugh Map Using Pairs of Adjacent Cells 3.5.2 Minimization of a Karnaugh Map Using Quads of Four Adjacent Cells 3.5.3 Minimization of a Karnaugh Map Using Octet of Eight Adjacent Cells 3.5.4 Minimization of a Karnaugh Map Using Offset Adjacencies and Diagonal Adjacencies 3.5.5 Minimization by Finding Prime Implicants 3.6 Drawing of Logic Circuit Using AND-OR Gates, OR-AND Gates, NAND’s Only, NOR’s Only 3.7 Representations of a Function (Cover) for a Computer-aided Minimization for Simplifying the Logic Circuits 3.7.1 Representation in Cube Format for Computer-aided Minimization 3.7.2 Representation in Four-Dimensional Hypercube Formats for a Computer-aided Minimization 3.7.3 Representation in Hypercube (Multi-dimensional cube) Formats for Computer-aided Minimization 3.8 Multi-Output Simplification 3.8.1 Prime Implicants for Multi-Outputs Case 3.9 Two Outputs Simplification–Computer-Based Prime Implicants Using Star Product and Sharp Operations 3.9.1 Combination of Two Cubes Differing in One Variable into One Cube—A Star Product Operation 3.9.2 Finding Essential Prime Implicants Using Two Cubes—A Sharp Operation 3.9.3 Computer-Based Minimization Method to Find Minimum Required Cover (SOP function implicants) 3.10 Computer-Based Minimization–Quine-McCluskey Method 3.10.1 Quine-McCluskey Method of Finding Prime Implicants 3.10.2 Finding Minimal Sum from the Prime Implicants for an Output 3.10.3 Finding Minimal Sum for the Multi-Output Case Using Quine-McCluskey Method Chapter 4: Binary Arithmetic and Decoding and Mux Logic Units 4.1 Binary Arithmetic Units 4.1.1 Binary Addition of Two Bits 4.1.2 Addition of Two Arithmetic Numbers Each of 4 Bits 4.1.3 Subtraction of Two Arithmetic Numbers Each of 4 Bits 4.2 Decoder 4.2.1 Decoder (Line Decoder) 4.2.2 The 1 of 2 and 1 of 4 Line Decoders 4.2.3 The Four-line to 16-line Decoder 4.2.4 Function Specific Decoders 4.3 Encoder 4.3.1 Encoder (Line Encoder) 4.3.2 Encoder (Priority Encoder) 4.3.3 BCD 10 of 1 Four-bit Encoder 4.3.4 Octal 8 of 1 Three-bit Encoder and Hexadecimal Encoder 4.4 Multiplexer 4.4.1 Multiplexer (Line Selector) 4.4.2 Multiplexer with Outputs Enabling Control (gate) Pin(s) 4.5 Demultiplexer 4.5.1 Demultiplexer Definition Chapter 5: Code Converters, Comparators and Other Logic Processing Circuits 5.1 Code Converters 5.1.1 Codes for Decimal Numbers 5.1.2 Unit Distance Code Converter 5.1.3 ASCII (American Standard Code for Information Interchange) for the Alphanumeric Characters 5.2 Equality and Magnitude Comparators Between Two Four-bit Numbers 5.3 Odd Parity and Even Parity Generators 5.4 The 4-bit AND, OR, XOR Between Two Words 5.4.1 AND 5.4.2 OR 5.4.3 XOR 5.4.4 Test Chapter 6: Sequential Logic, Latches and Flip-Flops 6.1 Flip Flop and Latch 6.2 Sr Latch (Set-Reset Latch) Using Cross Coupled NANDs 6.2.1 SR Latch at Various Input Conditions 6.2.2 Difficulties in Using an SR Latch 6.2.3 Timing Diagrams of an SR Latch 6.2.4 Level Clocked SR Latch 6.3 JK Flip-Flop 6.3.1 Explanation of the State Table for the Logic Circuit of an Edge-Triggered JK FF 6.4 T Flip-Flop 6.4.1 T Flip-Flop with Clear and Preset 6.5 D Flip-Flop and Latch 6.5.1 D Flip-Flop 6.5.2 D Flip-Flop with Clear and Preset 6.5.3 D Latch 6.6 Master-Slave RS Flip-Flop 6.7 Master-Slave (Pulse Triggered) JK Flip-Flop 6.7.1 MS JK Flip-Flop with Clear and Preset 6.8 Clock Inputs 6.8.1 Level Clocking of a Clock Input 6.8.2 Edge Triggering at a Clock Input 6.9 Pulse Clocking of the Latches in the Flip-Flops 6.10 Characteristic Equations for the Analysis Chapter 7: Sequential Circuits Analysis, State Minimization, State Assignment and Circuit Implementation 7.1 General Sequential Circuit with a Memory Section and Combinational Circuits at the Input and Output Stages 7.2 Synchronous and Asynchronous Sequential Circuits 7.2.1 Synchronous Sequential Circuit 7.2.2 Asynchronous Sequential Circuits 7.3 Clocked Sequential Circuit 7.4 Classification of Sequential Circuit as Moore and Mealy State Machine Circuits 7.4.1 Classification of a Sequential Circuit as Moore Model Circuit 7.4.2 Classification of a Sequential Circuit as Mealy Model Circuit 7.5 Analysis Procedure 7.5.1 Excitation Table 7.5.2 Transition Table 7.5.3 State Table 7.5.4 State Diagram 7.6 Conditions of States Equivalency 7.6.1 State Reduction and Minimization Procedure 7.6.2 Assignment of Variables to a State 7.7 Implementation Procedure Chapter 8: Sequential Circuits for Registers and Counters 8.1 Registers 8.1.1 Bi-stable Latches as the Register 8.1.2 Parallel-In Parallel-Out Buffer Register 8.1.3 Number of Bits in a Register 8.2 Shift Registers 8.2.1 Serial-In Serial-Out (SISO) Unidirectional Shift Register 8.2.2 Serial-In Parallel-Out (SIPO) Right Shift Register 8.2.3 Parallel-In Serial-Out (PISO) Right Shift Register 8.3 Counter 8.4 Ripple Counter 8.4.1 Cascaded Divide-By-2n Circuit as a Ripple Counter 8.4.2 Modulo-6, Modulo-7 and Modulo-10 Counters 8.4.3 Ring Counter 8.4.4 Johnson Counter (Even Sequences Switch Tail or Twisted Ring Counter) 8.4.5 Odd Sequencer Johnson Counter (Odd Sequencer Switch Tail or Twisted Ring Counter) 8.5 Synchronous Counter 8.5.1 Synchronous Counter Using Additional Logic Circuit 8.6 Asynchronous Clear, Preset and Load (JAM) in a Counter 8.7 Synchronous Clear, Preset and Load Facilities in a Counter 8.8 Timing Diagrams Chapter 9: Fundamental Mode Sequential Circuits 9.1 General Asynchronous Sequential Circuit 9.2 Unstable Circuit Operation 9.3 Stable Circuit Asynchronous Mode Operation 9.4 Fundamental Mode Asynchronous Circuit 9.4.1 Tabular Representation of Excitation-cum-Transitions of States and Outputs 9.5 Analysis Procedure 9.5.1 Excitation Table 9.5.2 Transition Table 9.5.3 State Table 9.5.4 State Diagram 9.5.5 Flow Table 9.5.6 Example of an Excitation-cum-Transition Table 9.5.7 Flow Table from Excitation-Transition Table 9.5.8 Flow Diagram 9.6 Races 9.6.1 Cycles of the Races 9.7 Race-Free Assignments Chapter 10: Hazards and Pulse Mode Sequential Circuits 10.1 Hazards 10.1.1 Static-0 Hazard 10.1.2 Static-1 Hazard 10.2 Identifying Static Hazards 10.2.1 Identification from the Boolean Expressions 10.2.2 Identification from the Karnaugh Map (Only One-variable Input Case) 10.2.3 Identification from the Karnaugh Map (Three-Variable Input) 10.2.4 Detecting Absence of Static 1 Hazard from the POS Form of Boolean Expression 10.2.5 Detecting Absence of Static 0 Hazard from the SOP Form of Boolean Expression 10.3 Eliminating Static Hazards 10.4 Dynamic Hazards 10.5 Hazards Free Circuits 10.6 Essential Hazards 10.7 Pulse Mode Sequential Circuit Chapter 11: Implementation of Combinational Logic by Standard ICs and Programmable ROM Memories 11.1 Standard ICs for Design Implementation 11.1.1 Adder/Subtractor IC and Magnitude Comparator 11.1.2 Decoder IC 11.1.3 Encoder IC 11.1.4 Multiplexer IC 11.2 Programming and Programmable Logic Memories 11.2.1 ROM (Pre-Programmed Read Only Memory) and PROM (Programmable Read Only Memory) Chapter 12: Implementation of Combinational Logic by Programmable Logic Devices 12.1 Basics Points to Remember When Using the PLDs (PROMs, PALs, PLAs) 12.2 PAL (Programmable Array Logic) 12.3 PLA (Programmable Logic Arrays) Chapter 13: Logic Gates 13.1 Revision of the Important Gates 13.2 Diode Circuit 13.3 Bipolar Junction Transistors and Mosfets 13.3.1 N-P-N Transistor Common Emitter Circuit 13.3.2 MOSFET Circuits 13.4 RTL, DTL, TTL Logic Gates 13.4.1 Resistor–Transistor Logic (RTL) 13.4.2 Diode–Transistor Logic (DTL) 13.4.3 Transistor–Transistor Logic (TTL) 13.4.4 TTL Other than NAND Gate 13.5 Emitter Coupled Logic (ECL) 13.5.1 ECL OR/NOR Gate 13.6 Integrated Injection Logic (I2L) 13.6.1 I2L Circuit Internal Connections 13.6.2 I2L Circuit Working 13.6.3 I2L Circuit Switching Speed, Delay Times and Power Dissipation 13.7 High Threshold Logic (HTL) 13.7.1 HTL Connections for the Output at F 13.7.2 Logic Operation for the Output at F 13.8 NMOS 13.8.1 NMOS Circuit Connections and Working 13.8.2 Calculation of Fan Out 13.8.3 Calculation of Propagation Delay 13.8.4 Calculation of Power Dissipation 13.8.5 NMOS Circuit Voltage Levels 13.8.6 Unconnected Input(s) not Permitted 13.9 CMOS 13.9.1 Importance and Features of CMOS Logic Circuits 13.9.2 Operations as Inverter (NOT), NOR and NAND 13.9.3 Calculation of Fan out 13.9.4 Calculation of Propagation Delay 13.9.5 Calculation of Power Dissipation 13.9.6 CMOS Circuit Voltage Levels 13.9.7 MOS Logic Circuits (CMOSs) and Their Relative Advantages with Respect to TTLs 13.10 Meanings of Speed , Propagation Delay, Operating Frequency, Power Dissipated per Gate, Supply Voltage Levels, Operational Voltage Levels that Define Logic States 1 and 0 13.11 Speed , Propagation Delay, Operating Frequency, Power Dissipated per Gate, Supply Voltage Levels, Operational Voltage Levels that Define Logic States ‘1’ and ‘0’ for Various Families of Gates Chapter 14: CPLDs and FPGAs 14.1 CPLDS 14.2 Registered PAL 14.3 Array Logic Cell 14.4 Field Programmable Gate Arrays (FPGAS) Chapter 15: VHDL—RTL Design, Combinational Logic, Data Types, and Operators 15.1 VHDL 15.1.1 VHDL Standard IEEE 1076 15.1.2 VHDL Standard IEEE 1164 15.1.3 VHDL Libraries 15.1.4 VHDL Identifiers, Keywords, and Comments 15.1.5 VHDL Data Objects 15.2 RTL Design 15.2.1 Data Flow Model 15.2.2 Port 15.2.3 Finite State Machine (FSM) 15.2.4 Entity in RTL Model 15.3 Behaviour Model for Process in an RTL Design 15.3.1 RTL Model Architecture 15.4 RTL Design for Combination Logic 15.5 Data Types 15.5.1 Subtypes 15.5.2 Array 15.5.3 Type Checking 15.6 Operators Chapter 16: VHDL—Packages, Sub Programs, and Sequential Circuits 16.1 Package 16.1.1 Package Declarations 16.1.2 Package Body 16.2 Subprograms 16.2.1 Procedure 16.2.2 Function 16.2.3 Attribute 16.3 Design Library 16.4 Sequential Circuits 16.4.1 General Sequential Circuit—Entity, Components, Architecture, and Processes 16.4.2 Synchronous Sequential Circuit 16.4.3 Sequencing Clock Circuit—Entity, Architecture and Processes 16.4.4 Clock inputs for Flip-flop and Latch Synchronous Sequential Circuits 16.4.5 Multiple Clock Signals from Main Clock Chapter 17: VHDL—Test Benches 17.1 Processes and Subprograms 17.1.1 Statements 17.1.2 Vectors 17.1.3 Conversions from a Data Type to another 17.1.4 Now and Wait 17.1.5 Files 17.1.6 Events and Sensitivity List 17.1.7 Assertion, Report, and Severity Functions 17.1.8 Instantiation During Structural Modeling 17.2 Testing of Combinational and Sequential Circuits 17.2.1 Testing of a Combinational Circuit 17.2.2 Testing of a Sequential Circuit 17.3 Test Benches Chapter 18: VHDL—Examples of Modeling of Adder, Counter, Flip-Flop, Finite State Machine, Multiplexer, and Demultiplexer 18.1 Adder 18.1.1 Adder Circuit 18.1.2 Test Bench for the Adder 18.2 Counter 18.2.1 Counter Circuit 18.2.2 Test Bench for the Counter 18.3 Flip-Flop 18.3.1 D-Flip-Flop 18.3.2 Test Bench for the D-Flip-Flop 18.3.3 JK-Flip-Flop 18.3.4 Test Bench for the JK-Flip-Flop 18.4 Finite State Machine 18.4.1 Finite State Machine Sequential Circuit 18.4.2 Test Bench for the Finite State Machine 18.5 Multiplexer 18.5.1 Multiplexer Circuit 18.5.2 Test Bench for the Multiplexer (2:1) 18.6 Demultiplexer 18.6.1 Demultiplexer Circuit 18.6.2 Test Bench for the Demultiplexer (2:1) Solved Question Papers Index