Multi-Gigahertz Nyquist Analog-to-Digital Converters. Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies

Description

Preface Acknowledgments Contents List of Figures List of Tables 1 Introduction 1.1 Data Converters in a Digital Era: Need and High-Performance Applications 1.2 Challenges in Pushing Performance Boundaries 1.2.1 ADC Core and Peripherals Challenges 1.2.2 The Good, the Bad, and the Ugly of Deep-Scaled CMOS 1.3 Research Goal and Objectives 1.4 Structure of This Book 2 Analog-to-Digital Conversion Fundamentals 2.1 Theoretical Background 2.1.1 Sampling 2.1.2 Ideal Quantization 2.2 Error Sources 2.2.1 Noise 2.2.2 Non-linearity 2.2.3 Calibration 2.3 Performance Evaluation 2.3.1 Metrics 2.3.2 Figures of Merit 2.4 Accuracy-Speed-Power Limits 2.4.1 Sampler Noise Limit 2.4.2 Quantizer Noise Limit 2.4.3 Metastability Limit 2.4.4 Aperture Jitter Limit 2.4.5 Mismatch Limit 2.4.6 Heisenberg Uncertainty Principle 2.4.7 Putting It All Together 2.5 Conclusion Appendix A: Proper FFT Evaluation Setup 3 Architectural Considerations for High-Efficiency GHz-Range ADCs 3.1 State of the Art 3.2 The Flash Architecture 3.2.1 Overview 3.2.2 Flash Accuracy-Speed-Power Limits 3.2.3 Impact of Scaling 3.3 The SAR Architecture 3.3.1 Overview 3.3.2 The DAC in a SAR 3.3.3 SAR Accuracy-Speed-Power Limits 3.4 The Pipeline Architecture 3.4.1 Overview 3.4.2 Pipeline Accuracy-Speed-Power Limits 3.5 The Pipelined-SAR: A Powerful Hybrid 3.5.1 Overview 3.5.2 Pipelined-SAR Accuracy-Speed-Power Limits 3.6 Architectural Limits' Comparison 3.7 Time-Interleaving 3.7.1 Overview 3.7.2 Interleaving Errors 3.7.3 Interleaver Architectures 3.8 Conclusion Appendix B: Transconductance—Settled RA Appendix C: Transconductance—Integrator RA 4 Ultrahigh-Speed High-Sensitivity Dynamic Comparator 4.1 Dynamic Regenerative Comparators 4.1.1 Single-Stage Latch-Based Strong-ARM Comparator 4.1.2 Two-Stage Double-Tail Latched Comparator 4.2 Prototype IC: A 28 nm CMOS Three-Stage Triple-Latch Feed-Forward Comparator 4.2.1 Circuit Operation and Analysis 4.2.2 Simulation and Comparison with Prior Art 4.2.3 On-Chip Delay Evaluation Setup 4.3 Experimental Verification 4.3.1 Measurement Setup 4.3.2 Measurement Results 4.3.3 State-of-the-Art Comparison 4.4 Conclusion 5 High-Speed Wide-Bandwidth Single-Channel SAR ADC 5.1 Pushing the SAR Conversion Speed 5.1.1 Conventional Synchronous Clocking Scheme 5.1.2 Speed-Boosting Techniques Asynchronous Processing Multi-bit per Cycle Loop Unrolling Redundancy Pipelining DAC Switching Schemes 5.2 Prototype IC: A 1.25 GS/s 7-bit SAR ADC in 28 nm CMOS 5.2.1 High-Level Design 5.2.2 Semi-asynchronous Processing w/o Logic Delay 5.2.3 Dual-Loop Bootstrapped Input Switch 5.2.4 Unit-Switch-Plus-Cap DAC 5.2.5 Triple-Tail Dynamic Comparator 5.2.6 Custom SAR Logic 5.3 Experimental Verification 5.3.1 Measurement Setup 5.3.2 Measurement Results 5.3.3 State-of-the-Art Comparison 5.4 Conclusion 6 High-Resolution Wide-Bandwidth Time-Interleaved RF ADC 6.1 RF Sampling ADCs: Needs and Challenges 6.1.1 The ADC Role in the Receiver 6.1.2 ADC Architectural Trade-Offs 6.2 Prototype IC: A 5 GS/s 12-bit Hybrid TI-ADC in 28 nm CMOS 6.2.1 High-Level Design 6.2.2 Interleaving Factor and Sub-ADC Architecture 6.2.3 Passive Input Front-End 6.2.4 Clock Generation and Distribution 6.2.5 Hybrid Sub-ADC Design 6.2.6 Digital Calibration 6.3 Experimental Verification 6.3.1 Measurement Setup 6.3.2 Measurement Results 6.3.3 State-of-the-Art Comparison 6.4 Conclusion Appendix D: TI ADC Power Estimation with On-Chip Input Buffer 7 Ultra-Wideband Direct RF Receiver Analog Front-End 7.1 Pushing the Bandwidth Beyond 20 GHz 7.1.1 Revisiting the Analog Front-End Problem 7.1.2 Increasing Integration and Challenges 7.2 Prototype IC: A 30 GHz-Bandwidth