Intel® 64 and IA-32 Architectures Software Developer’s Manual

Description

Revision History Preface Summary Tables of Changes Documentation Changes 1. Updates to Chapter 1, Volume 1 Chapter 1 About This Manual 1.1 Intel® 64 and IA-32 Processors Covered in this Manual 1.2 Overview of Volume 1: Basic Architecture 1.3 Notational Conventions 1.3.1 Bit and Byte Order 1.3.2 Reserved Bits and Software Compatibility 1.3.2.1 Instruction Operands 1.3.3 Hexadecimal and Binary Numbers 1.3.4 Segmented Addressing 1.3.5 A New Syntax for CPUID, CR, and MSR Values 1.3.6 Exceptions 1.4 Related Literature 2. Updates to Chapter 5, Volume 1 Chapter 5 Instruction Set Summary 5.1 General-Purpose Instructions 5.1.1 Data Transfer Instructions 5.1.2 Binary Arithmetic Instructions 5.1.3 Decimal Arithmetic Instructions 5.1.4 Logical Instructions 5.1.5 Shift and Rotate Instructions 5.1.6 Bit and Byte Instructions 5.1.7 Control Transfer Instructions 5.1.8 String Instructions 5.1.9 I/O Instructions 5.1.10 Enter and Leave Instructions 5.1.11 Flag Control (EFLAG) Instructions 5.1.12 Segment Register Instructions 5.1.13 Miscellaneous Instructions 5.1.14 User Mode Extended Sate Save/Restore Instructions 5.1.15 Random Number Generator Instructions 5.1.16 BMI1, BMI2 5.1.16.1 Detection of VEX-encoded GPR Instructions, LZCNT and TZCNT, PREFETCHW 5.2 x87 FPU Instructions 5.2.1 x87 FPU Data Transfer Instructions 5.2.2 x87 FPU Basic Arithmetic Instructions 5.2.3 x87 FPU Comparison Instructions 5.2.4 x87 FPU Transcendental Instructions 5.2.5 x87 FPU Load Constants Instructions 5.2.6 x87 FPU Control Instructions 5.3 x87 FPU AND SIMD State Management Instructions 5.4 MMX™ Instructions 5.4.1 MMX Data Transfer Instructions 5.4.2 MMX Conversion Instructions 5.4.3 MMX Packed Arithmetic Instructions 5.4.4 MMX Comparison Instructions 5.4.5 MMX Logical Instructions 5.4.6 MMX Shift and Rotate Instructions 5.4.7 MMX State Management Instructions 5.5 SSE Instructions 5.5.1 SSE SIMD Single-Precision Floating-Point Instructions 5.5.1.1 SSE Data Transfer Instructions 5.5.1.2 SSE Packed Arithmetic Instructions 5.5.1.3 SSE Comparison Instructions 5.5.1.4 SSE Logical Instructions 5.5.1.5 SSE Shuffle and Unpack Instructions 5.5.1.6 SSE Conversion Instructions 5.5.2 SSE MXCSR State Management Instructions 5.5.3 SSE 64-Bit SIMD Integer Instructions 5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions 5.6 SSE2 Instructions 5.6.1 SSE2 Packed and Scalar Double-Precision Floating-Point Instructions 5.6.1.1 SSE2 Data Movement Instructions 5.6.1.2 SSE2 Packed Arithmetic Instructions 5.6.1.3 SSE2 Logical Instructions 5.6.1.4 SSE2 Compare Instructions 5.6.1.5 SSE2 Shuffle and Unpack Instructions 5.6.1.6 SSE2 Conversion Instructions 5.6.2 SSE2 Packed Single-Precision Floating-Point Instructions 5.6.3 SSE2 128-Bit SIMD Integer Instructions 5.6.4 SSE2 Cacheability Control and Ordering Instructions 5.7 SSE3 Instructions 5.7.1 SSE3 x87-FP Integer Conversion Instruction 5.7.2 SSE3 Specialized 128-bit Unaligned Data Load Instruction 5.7.3 SSE3 SIMD Floating-Point Packed ADD/SUB Instructions 5.7.4 SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions 5.7.5 SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions 5.7.6 SSE3 Agent Synchronization Instructions 5.8 Supplemental Streaming SIMD Extensions 3 (SSSE3) Instructions 5.8.1 Horizontal Addition/Subtraction 5.8.2 Packed Absolute Values 5.8.3 Multiply and Add Packed Signed and Unsigned Bytes 5.8.4 Packed Multiply High with Round and Scale 5.8.5 Packed Shuffle Bytes 5.8.6 Packed Sign 5.8.7 Packed Align Right 5.9 SSE4 Instructions 5.10 SSE4.1 Instructions 5.10.1 Dword Multiply Instructions 5.10.2 Floating-Point Dot Product Instructions 5.10.3 Streaming Load Hint Instruction 5.10.4 Packed Blending Instructions 5.10.5 Packed Integer MIN/MAX Instructions 5.10.6 Floating-Point Round Instructions with Selectable Rounding Mode 5.10.7 Insertion and Extractions from XMM Registers 5.10.8 Packed Integer Format Conversions 5.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks 5.10.10 Horizontal Search 5.10.11 Packed Test 5.10.12 Packed Qword Equality Comparisons 5.10.13 Dword Packing With Unsigned Saturation 5.11 SSE4.2 Instruction Set 5.11.1 String and Text Processing Instructions 5.11.2 Packed Comparison SIMD integer Instruction 5.12 Intel® AES-NI and PCLMULQDQ 5.13 Intel® Advanced Vector Extensions (Intel® AVX) 5.14 16-bit Floating-Point Conversion 5.15 Fused-Multiply-ADD (FMA) 5.16 Intel® Advanced Vector Extensions 2 (Intel® AVX2) 5.17 Intel® Transactional Synchronization Extensions (Intel® TSX) 5.18 Intel® SHA Extensions 5.19 Intel® Advanced Vector Extensions 512 (Intel® AVX-512) 5.20 System Instructions 5.21 64-Bit Mode Instructions 5.22 Virtual-Machine Extensions 5.23 Safer Mode Extensions 5.24 Intel® Memory Protection Extensions 5.25 Intel® Software Guard Extensions 5.26 Shadow Stack Management Instructions 5.27 Control Transfer Terminating Instructions 3. Updates to Chapter 10, Volume 1 Chapter 10 Programming with Intel® Streaming SIMD Extensions (Intel® SSE) 10.1 Overview of SSE Extensions 10.2 SSE Programming Environment 10.2.1 SSE in 64-Bit Mode and Compatibility Mode 10.2.2 XMM Registers 10.2.3 MXCSR Control and Status Register 10.2.3.1 SIMD Floating-Point Mask and Flag Bits 10.2.3.2 SIMD Floating-Point Rounding Control Field 10.2.3.3 Flush-To-Zero 10.2.3.4 Denormals-Are-Zeros 10.2.4 Compatibility of SSE Extensions with SSE2/SSE3/MMX and the x87 FPU 10.3 SSE Data Types 10.4 SSE Instruction Set 10.4.1 SSE Packed and Scalar Floating-Point Instructions 10.4.1.1 SSE Data Movement Instructions 10.4.1.2 SSE Arithmetic Instructions 10.4.2 SSE Logical Instructions 10.4.2.1 SSE Comparison Instructions 10.4.2.2 SSE Shuffle and Unpack Instructions 10.4.3 SSE Conversion Instructions 10.4.4 SSE 64-Bit SIMD Integer Instructions 10.4.5 MXCSR State Management Instructions 10.4.6 Cacheability Control, Prefetch, and Memory Ordering Instructions 10.4.6.1 Cacheability Control Instructions 10.4.6.2 Caching of Temporal vs. Non-Temporal Data 10.4.6.3 PREFETCHh Instructions 10.4.6.4 SFENCE Instruction 10.5 FXSAVE and FXRSTOR Instructions 10.5.1 FXSAVE Area 10.5.1.1 x87 State 10.5.1.2 SSE State 10.5.2 Operation of FXSAVE 10.5.3 Operation of FXRSTOR 10.6 Handling SSE Instruction Exceptions 10.7 Writing Applications with the SSE Extensions 4. Updates to Chapter 15, Volume 1 Chapter 15 Programming with Intel® AVX-512 15.1 Overview 15.1.1 512-Bit Wide SIMD Register Support 15.1.2 32 SIMD Register Support 15.1.3 Eight Opmask Register Support 15.1.4 Instruction Syntax Enhancement 15.1.5 EVEX Instruction Encoding Support 15.2 Detection of AVX-512 Foundation Instructions 15.2.1 Additional 512-bit Instruction Extensions of the Intel AVX-512 Family 15.3 Detection of 512-bit Instruction Groups of Intel® AVX-512 Family 15.4 Detection of Intel AVX-512 Instruction Groups Operating at 256 and 128-bit Vector Lengths 15.5 Accessing XMM, YMM AND ZMM Registers 15.6 Enhanced Vector Programming Environment Using EVEX Encoding 15.6.1 OPMASK Register to Predicate Vector Data Processing 15.6.1.1 Opmask Register K0 15.6.1.2 Example of Opmask Usages 15.6.2 OpMask Instructions 15.6.3 Broadcast 15.6.4 Static Rounding Mode and Suppress All Exceptions 15.6.5 Compressed Disp8*N Encoding 15.7 Memory Alignment 15.8 SIMD Floating-Point Exceptions 15.9 Instruction Exception Specification 15.10 Emulation 15.11 Writing floating-point exception handlers 5. Updates to Chapter 1, Volume 2A Chapter 1 About This Manual 1.1 Intel® 64 and IA-32 Processors Covered in this Manual 1.2 Overview of Volume 2A, 2B, 2C and 2D: Instruction Set Reference 1.3 Notational Conventions 1.3.1 Bit and Byte Order 1.3.2 Reserved Bits and Software Compatibility 1.3.3 Instruction Operands 1.3.4 Hexadecimal and Binary Numbers 1.3.5 Segmented Addressing 1.3.6 Exceptions 1.3.7 A New Syntax for CPUID, CR, and MSR Values 1.4 Related Literature 6. Updates to Chapter 2, Volume 2A Chapter 2 Instruction Format 2.1 Instruction Format for Protected Mode, real-address Mode, and virtual-8086 mode 2.1.1 Instruction Prefixes 2.1.2 Opcodes 2.1.3 ModR/M and SIB Bytes 2.1.4 Displacement and Immediate Bytes 2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes 2.2 IA-32e Mode 2.2.1 REX Prefixes 2.2.1.1 Encoding 2.2.1.2 More on REX Prefix Fields 2.2.1.3 Displacement 2.2.1.4 Direct Memory-Offset MOVs 2.2.1.5 Immediates 2.2.1.6 RIP-Relative Addressing 2.2.1.7 Default 64-Bit Operand Size 2.2.2 Additional Encodings for Control and Debug Registers 2.3 Intel® Advanced Vector Extensions (Intel® AVX) 2.3.1 Instruction Format 2.3.2 VEX and the LOCK prefix 2.3.3 VEX and the 66H, F2H, and F3H prefixes 2.3.4 VEX and the REX prefix 2.3.5 The VEX Prefix 2.3.5.1 VEX Byte 0, bits[7:0] 2.3.5.2 VEX Byte 1, bit [7] - ‘R’ 2.3.5.3 3-byte VEX byte 1, bit[6] - ‘X’ 2.3.5.4 3-byte VEX byte 1, bit[5] - ‘B’ 2.3.5.5 3-byte VEX byte 2, bit[7] - ‘W’ 2.3.5.6 2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or Dest Register Specifier 2.3.6 Instruction Operand Encoding and VEX.vvvv, ModR/M 2.3.6.1 3-byte VEX byte 1, bits[4:0] - “m-mmmm” 2.3.6.2 2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L” 2.3.6.3 2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp” 2.3.7 The Opcode Byte 2.3.8 The MODRM, SIB, and Displacement Bytes 2.3.9 The Third Source Operand (Immediate Byte) 2.3.10 AVX Instructions and the Upper 128-bits of YMM registers 2.3.10.1 Vector Length Transition and Programming Considerations 2.3.11 AVX Instruction Length 2.3.12 Vector SIB (VSIB) Memory Addressing 2.3.12.1 64-bit Mode VSIB Memory Addressing 2.4 AVX and SSE Instruction Exception Specification 2.4.1 Exceptions Type 1 (Aligned memory reference) 2.4.2 Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned) 2.4.3 Exceptions Type 3 (=16 Byte mem arg, no alignment, no floating-point exceptions) 2.4.5 Exceptions Type 5 (