Principles of Simulation of VHDL models in WebPack
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ХНУРЭ, Сыревич Е. Е., для студентов Центра обучения на иностранном языке, язык - англ.topic: Simulation is a process of driving certain input values (stimuli or tests) on the inputs of your model and checking the results which come from the outputs of the model.assignment:Create two models of xor_gate: with and without delay operator. Simulate both models with the given timing. Your target is to obtain simulation results as it was shown.Change the input stimuli to be the following Repeat both simulations (for the code with delay and for the code without it).Prepare your report. you have to report the following: the truth table, the interface with inputs and outputs, the vhdl model with comments, the results of synthesis in webpack software. Also explain the waveforms manually (4 waveforms all together). Compare them very carefully
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