PCI Express ExpressModule Electromechanical Specification, Revision 1.0

Description

Contents 1. Introduction 1.1. Terms and Definitions 1.2. Reference Documents 1.3. Specification Contents 1.4. Objectives 1.5. Overview 2. ExpressModule Auxiliary Interfaces 2.1. Reference Clock 2.1.1. Low Voltage Swing, Differential Clocks 2.1.2. Spread Spectrum Clocking (SSC) 2.1.3. REFCLK Specifications 2.1.4. REFCLK Phase Jitter Specification 2.2. MRST# Signal 2.3. WAKE Signal 2.4. Internal Storage Interface 2.4.1. Storage Interface Signal Definitions 2.4.1.1. High Speed SAS/SATA Channels 2.4.1.2. Storage Sideband Signals – I2C/SMBus or SGPIO 2.5. Power Management 2.5.1. Initial Power-Up (G3 to L0) 2.5.2. Power Management States (S0 to S3/S4 to S0) 2.5.3. Power Down 2.6. Management 2.6.1. Capacitive Load of High-power SMBus Lines 2.6.2. Minimum Current Sinking Requirements for SMBus Devices 2.6.3. SMBus “Back Powering” Considerations 2.6.4. Power-on Reset 2.6.5. SMBus Termination and Power 2.6.6. SMBAlert 2.6.7. Management Bus Topology 2.6.8. Data Integrity 2.6.9. Basic Management Status Register 2.6.10. Satellite Management Controller 2.6.11. Remote Management Card Access 2.6.12. VPD (FRU) Information Format 2.6.12.1. VPD (FRU) Record Format 2.6.12.2. Record Header Fields 2.6.12.3. Board Info Record 2.6.12.4. Product Info Record 2.6.12.5. Product GUID Record 2.6.12.6. ExpressModule Module Info Record 2.6.12.7. PCI Express Device Info Record 2.6.12.8. ExpressModule Multiplexer Record 2.6.12.9. OEM Records 2.6.12.10. Language Codes 2.6.12.11. Type/Length Byte Format 2.6.12.11.1. BCD Plus Definition 2.6.12.11.2. 6-bit ASCII Definition 2.6.12.11.3. 6-bit ASCII Packing Example 2.6.13. Using an SMBus Multiplexer with a Host Controller 2.6.14. Implementing ExpressModule Management in an IPMI Environment 2.6.14.1. Slave Attention-based Protocol 2.6.14.2. Peer-to-Peer Proxy Messaging 2.6.15. Sending Data to a Management Controller on a Module 2.6.15.1. Single-part Write Protocol 2.6.15.2. Multi-part Write Protocol 2.6.15.3. Error Conditions for Multi-part Writes 2.6.16. Receiving Data From a Management Controller on a Module 2.6.16.1. Single-part Read Protocol 2.6.16.2. Multi-part Read Protocol 2.6.17. SMBAlert Control and Status 2.6.17.1. Get Message Interface Status 2.6.17.2. Set Message Interface Control 2.6.18. Message Class Values for Management Controller Messaging 2.6.19. Retention of Output Data 2.6.20. SMBAlert Signal Handling for Message Transfers 2.6.21. Polling for Output Data 2.6.22. SMBus NACKs and Error Recovery 2.6.23. PEC Handling 2.6.24. Summary of SMBus Commands Values for Management Controller Messaging 2.6.25. SMBus Timeout and Hang Handling 2.6.26. Management Controller Messaging Timing 2.6.27. IPMI Management Controller Message Formats 2.6.27.1. BMC to Module IPMI Message Format Examples 2.6.27.2. Module to BMC IPMI Message Format Examples 2.6.28. Pre-assigned/Reserved Slave Addresses 2.7. Auxiliary Signal Parametric Specifications 2.7.1. DC Specifications 2.7.2. AC Specifications 3. Hot Insertion/Removal 3.1. Scope 3.2. Hot-Plug Sub-System Architecture 3.2.1. Power Enable 3.2.2. Power Fault 3.2.3. Wake 3.2.4. Module Power Good 3.2.5. Module Reset 3.2.6. Present Detection 3.2.7. System Management Bus 3.2.8. System Management Bus Alert 3.2.9. Power LED 3.2.10. Attention LED 3.2.11. Manual Retention Latch 3.2.12. Electromechanical Interlock 3.2.13. Electromechanical Interlock Status 3.2.14. Attention Switch 4. Module Power Interface 4.1. Power 4.1.1. Module Primary Power Supply 4.1.2. Module Auxiliary Power Supply 4.2. ExpressModule Power Supply Requirements 4.3. Power Consumption 4.4. Power Supply Sequencing 4.5. Power Supply Decoupling 5. Module PCI Express Interface 5.1. PCI Express Link Signals 5.2. PCI Express Electrical Topologies and Link Definitions 5.2.1. Topologies 5.2.2. Link Definitions 5.3. PCI Express Electrical Budgets 5.3.1. AC Coupling Capacitors 5.3.2. Insertion Loss Values (Voltage Transfer Function) 5.3.3. Jitter Values 5.3.4. Crosstalk 5.3.5. Lane-to-Lane Skew 5.3.6. Equalization 5.3.7. Skew Within the Differential Pair 5.4. Eye Diagrams at the ExpressModule Interface 5.4.1. ExpressModule Transmitter Path Compliance Eye Diagram 5.4.2. ExpressModule Minimum Receiver Path Sensitivity Requirements 5.4.3. System Board Transmitter Path Compliance Eye Diagram 5.4.4. System Board Minimum Receiver Path Sensitivity Requirements 6. ExpressModule Connector 6.1. Connector Pin Counts 6.2. Connector Pin Assignments 6.3. Connector Interface Definitions 6.4. Connector Signal Integrity Requirements and Test Procedures 6.5. Connector Environmental and Other Requirements 6.5.1. Environmental Requirements 6.5.2. Mechanical Requirements 6.5.3. Current Rating Requirement 6.5.4. Additional Considerations 7. Module Mechanical Specification 7.1. Mechanical Overview 7.2. Dimensions and Tolerances 7.3. System Datum Plane Definition 7.4. Module Description 7.4.1. Module Materials 7.4.1.1. Conductivity Measurement Procedure 7.4.1.2. Corrosion Measurement Procedure 7.4.2. Singlewide and Doublewide Module Form Factor 7.4.3. Module Raw Card 7.4.4. Module Ejector and Latch Details 7.4.5. I/O Plate Details 7.4.6. Module Air Vent Design for EMI 7.5. Filler Component or Module 7.6. Chassis Slot Description 7.6.1. Backplane and Chassis Slot Details 7.6.1.1. Chassis Slot EMI Design 8. Design Considerations 8.1. Cooling/Thermal Environment 8.1.1. Longitudinal Cooling – Default Mode 8.1.1.1. Airflow Supplied to Module – Default Mode 8.1.1.2. Module Pressure Drop – Default Mode 8.1.2. Lateral Cooling – Alternate Mode 8.1.2.1. Air Re-circulation Barrier – Closed Vent Operation 8.1.2.2. Airflow Supplied to Module – Alternate Mode 8.1.2.3. Series Modules 8.1.2.4. Module Pressure Drop – Alternate Mode 8.1.3. Cooling Consideration for Storage Extension Slot 8.1.4. Module EMI Design 8.2. Module ESD Design 8.3. Module Interoperability 8.4. Slot/Module Color Coding and Labeling 8.4.1. Module Hot Remove and Add Capability 8.4.2. Modules That May Require a System Power Down 8.4.3. Internal Storage Modules 8.4.4. Optional Module Labeling 8.4.5. Slot Labeling on the System 8.4.6. Optional x16 Doublewide Slot Labeling 8.4.7. Slot Numbering and Labeling 8.4.7.1. Slot Numbering 8.4.7.2. Vent Designation