Model and design of improved current mode logic gates : differential and single-ended

Description

Preface Acknowledgements Contents About the Authors 1 Introduction 1.1 Background 1.2 Current Mode Logic References 2 Current Mode Logic (CML): Basic Concepts 2.1 Introduction 2.2 Basic Concepts 2.3 Differential CML Gates 2.3.1 Analysis of Differential CML Gates 2.3.2 Design of a Differential CML Inverter 2.3.3 Analysis of Two-Level CML Gates 2.4 Single-Ended CML Gates 2.4.1 PFSCL Gates 2.4.2 Analysis of a PFSCL Inverter 2.4.3 Design of a PFSCL Inverter 2.5 Summary References 3 Differential CML Gates with Modified PDN 3.1 Introduction 3.2 Triple-Tail Cell-Based Approach 3.3 Triple-Tail Cell (TT-1)-Based Differential CML Gates 3.3.1 Analysis of TT-1-Based CML Gates 3.3.2 Design of TT-1-Based CML Gates 3.3.3 Performance Comparison 3.3.4 Extension to D Latch Design 3.4 Triple-Tail Cell (TT-2)-Based Differential CML Gates 3.4.1 Analysis of TT-2 Based CML Gates 3.4.2 Design of TT-2-Based CML Gates 3.4.3 Performance Comparison 3.5 Summary References 4 CML Gates with Modified Current Source 4.1 Introduction 4.2 Dynamic CML Gates 4.3 Dynamic Differential CML Gates 4.3.1 Dy-DCML-NN Gates 4.3.1.1 Operation of a Dy-DCML-NN Inverter 4.3.1.2 Design of a Dy-DCML-NN Inverter 4.3.1.3 Power Consumption of Dy-DCML-NN Gates 4.3.1.4 Design Examples 4.3.2 Dy-DCML-NP Gates 4.3.2.1 Operation of a Dy-DCML-NP Inverter 4.3.2.2 Design of Dy-DCML-NP Inverter 4.3.2.3 Power Consumption of Dy-DCML-NP Gates 4.3.2.4 Design Examples 4.3.3 General Discussion on Dynamic Differential CML Gate 4.4 Dynamic PFSCL Gates 4.4.1 Dy-PFSCL-NN Gates 4.4.1.1 Operation of a Dy-PFSCL-NN Inverter 4.4.1.2 Design of Dy-PFSCL-NN Gates 4.4.1.3 Power Consumption of a Dy-PFSCL-NN Gate 4.4.1.4 Design Examples 4.4.2 Dy-PFSCL-NP Gates 4.4.2.1 Operation of Dy-PFSCL-NP Inverter 4.4.2.2 Design of Dy-PFSCL-NP Inverter 4.4.2.3 Power Consumption of Dy-PFSCL-NP Gates 4.4.2.4 Design Examples 4.4.3 General Discussion on Dy-PFSCL Gates 4.5 Multi-stage Applications 4.5.1 Multi-stage D-CML Design Using STB-1 4.5.2 Multi-stage D-CML Design Using STB-2 4.6 Performance Comparison with Static Gates 4.6.1 Performance Comparison of Differential CML Gates 4.6.2 Performance Comparison of PFSCL Gates 4.7 Summary References 5 CML Gates with Modified Load 5.1 Introduction 5.2 Available Loads 5.3 NP-Load 5.3.1 Analysis of NP-Load 5.3.2 Resistance of NP-Load 5.4 Differential CML Gates with NP-Load (CML-CC) 5.4.1 Operation of Differential CML-CC Inverter 5.4.2 Analysis of Differential CML-CC Inverter 5.4.2.1 Static Model 5.4.2.2 Delay Model 5.4.3 Design of Differential CML-CC Inverter 5.4.4 Performance Comparison 5.5 PFSCL Gates with Modified NP-Load (PFSCL-CC) 5.5.1 Operation of PFSCL-CC Inverter 5.5.2 Analysis of PFSCL-CC Inverter 5.5.2.1 Static Model 5.5.2.2 Delay Model 5.5.3 Design of PFSCL-CC Inverter 5.5.4 Performance Comparison 5.6 Summary References 6 PFSCL Circuits with Reduced Gate Count 6.1 Introduction 6.2 Realization of PFSCL Circuits (Method-1) 6.3 Realization of PFSCL Circuits (Method-2) 6.3.1 Analysis of Fundamental Cell 6.3.2 Design of Fundamental Cell 6.3.3 Basic Gate Realization 6.4 Performance Comparison 6.5 Design Examples 6.5.1 LFSR Design 6.5.2 Adder Design 6.6 Summary References 7 Tri-state CML Circuits 7.1 Introduction 7.2 Differential Tri-state CML Circuits 7.2.1 Switch-Based Differential Tri-state CML Circuit 7.2.2 Voltage Follower-Based Differential Tri-state CML Circuit 7.2.3 Low-Power Differential Tri-state CML Circuit 7.2.4 Performance Comparison 7.2.5 Application Examples 7.2.5.1 Bus System Implementation 7.2.5.2 D Latch Implementation 7.3 Tri-state PFSCL Circuits 7.3.1 Switch-Based Tri-state PFSCL Circuits 7.3.1.1 Tri-state PFSCL Circuit with Modified Load Section (Topology 1) 7.3.1.2 Tri-state PFSCL Circuits with Modified Current Source Section 7.3.1.3 Performance Comparison 7.3.1.4 Bus Implementation 7.3.2 Sleep Transistor-Based PFSCL Tri-state Circuits 7.3.2.1 Issue in Bus Implementation 7.3.2.2 Improved Sleep Transistor-Based PFSCL Tri-state Topologies 7.3.2.3 Performance Comparison 7.4 Summary References