Resource Efficient LDPC Decoders: From Algorithms to Hardware Architectures

Description

Resource Efficient LDPC Decoders 6007bba2-1a4b-4d66-b674-02154ad3f8e3.pdf Copyright a7aa712e-6e15-48cf-abbe-4fa510a9ccdb.pdf About the Authors cbb71384-c788-4070-93fd-3a8b71acedad.pdf Acknowledgements 6c338e05-9132-46c2-bb08-8284cbe1eb4b.pdf Preface 5b85375c-ff58-4585-a5b1-8531946e35d2.pdf List of Abbreviations 8d7374d9-9bd1-4ae4-bbbf-65b5cf26aada.pdf 1 Introduction 1.1 Error Correction in Digital Communication System 1.2 Forward Error Correction Codes References f8cdf7b2-b813-4e13-a18c-8004c5a39bf6.pdf 2 Overview of LDPC codes 2.1 Origin of LDPC Codes 2.2 Types of LDPC Codes 2.2.1 Regular and irregular codes 2.2.2 Random and pseudo-random codes 2.2.3 Structured and Unstructured Codes 2.3 Terminologies in LDPC Codes 2.3.1 LDPC code parameters 2.3.2 Simulation parameters 2.3.3 Performance metrics 2.4 Summary References 43a75fa2-0e51-4529-a674-3eb813680967.pdf 3 Structure and flexibility of LDPC codes 3.1 LDPC Code Construction 3.1.1 Progressive edge growth codes 3.1.2 Quasi-cyclic codes 3.1.3 Spatially-coupled codes 3.1.4 Repeat-accumulate codes 3.2 Flexible Codes 3.2.1 Structure of the matrix 3.2.2 Construction technique 3.2.3 Standard matrix configurations 3.2.4 Visual analysis 3.2.5 Performance analysis 3.3 Summary References 41a7e870-eeeb-4421-8974-4fcb88d5b6c6.pdf 4 LDPC decoding algorithms 4.1 Standard Decoding Algorithms 4.1.1 Bit-Flip algorithm 4.1.2 Sum-Product algorithm 4.1.3 Min-sum algorithm 4.1.4 Stochastic algorithm 4.2 Reduced Complexity Algorithms 4.2.1 Simplified message passing 4.2.1.1 Check node operation 4.2.1.2 Variable node operation 4.2.2 Modified Min-Sum 4.2.2.1 Variable node operation 4.2.2.2 Check node operation 4.3 Performance Analysis of Simplified Algorithms 4.3.1 Extraction of optimized parameters 4.3.2 Performance comparison 4.4 Summary References ac6471d4-8505-475b-a6cb-2cdcc219a504.pdf 5 LDPC decoder architectures 5.1 Common Hardware Architectures 5.1.1 Fully-parallel 5.1.2 Fully-serial 5.1.3 Partially-parallel 5.2 Review of Practical LDPC Decoders 5.3 Summary References c7f772ee-72e6-49ba-b78a-245d215f77db.pdf 6 Hardware implementation of LDPC decoders 6.1 Decoder Design Methodology 6.1.1 Design and implementation 6.1.2 Performance measurement 6.2 Prototyping LDPC Codes in Hardware 6.3 Implementation of Hardware Efficient Decoder 6.3.1 Fully-parallel architecture 6.3.1.1 Simplified message passing decoder 6.3.1.2 Modified Min-Sum decoder 6.3.2 Partially-parallel architecture 6.3.3 Performance analysis 6.4 Design Space Exploration 6.4.1 Decoding performance 6.4.2 Hardware performance 6.5 Summary References e8032770-548c-4ce9-b50c-a4aabc2c8621.pdf 7 LDPC decoders in multimedia communication 7.1 Image Communication Using LDPC Codes 7.2 Performance Analysis 7.2.1 Quality of the reconstructed BMP images 7.2.2 Quality of the reconstructed JPEG images 7.2.3 Reconstructed JPEG images for various decoders 7.3 Summary References e53ebaf6-4196-4dbf-9b21-e0f196c5d20c.pdf 8 Prospective LDPC applications 8.1 Wireless Communication 8.2 Optical Communication 8.3 Flash Memory Devices References 76159fac-1cb5-4f4f-bbd0-1550573faef4.pdf Appendix A Sample C-Programs and MATLAB models for LDPC code construction and simulation 3cfe6e58-e810-4cf9-9a6d-080b97d41a51.pdf Appendix B Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architecture 80dfbd64-d0ef-4cc0-8097-665e191cb758.pdf Appendix C Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture ab3b9d1e-8676-4703-a778-3804b97b106c.pdf Index