Embedded Multimedia Security Systems: Algorithms And Architectures

Description

Opening with a detailed review of existing techniques for selective encryption, this text then examines algorithms that combine both encryption and compression. The book also presents a selection of specific examples of the design and implementation of secure embedded multimedia systems. Features: reviews the historical developments and latest techniques in multimedia compression and encryption; discusses an approach to reduce the computational cost of multimedia encryption, while preserving the properties of compressed video; introduces a polymorphic wavelet architecture that can make dynamic resource allocation decisions according to the application requirements; proposes a light-weight multimedia encryption strategy based on a modified discrete wavelet transform; describes a reconfigurable hardware implementation of a chaotic filter bank scheme with enhanced security features; presents an encryption scheme for image and video data based on chaotic arithmetic coding. Embedded Multimedia Security Systems......Page 2 Foreword......Page 5 Intended Audience......Page 6 Acknowledgements......Page 8 Contents......Page 9 Acronyms......Page 13 Part I: Multimedia Systems......Page 14 1.1 Video Coding......Page 15 1.2 Embedded Systems and Reconfigurable Architectures......Page 18 1.3 Encryption Basics......Page 20 2.1 Introduction......Page 22 2.2 Multimedia Encryption Problem......Page 23 2.3.1 Scrambling......Page 24 2.3.2 Post-compression Encryption Algorithm......Page 28 2.3.4 Selective Encryption......Page 30 2.3.6 Future of JVCE Schemes......Page 32 References......Page 33 Wireless Video Surveillance Networks......Page 34 3.2 Basics......Page 35 Related Research Efforts......Page 36 3.3 Our Approach......Page 37 How Exactly Can We Augment Encryption to Video Coding System?......Page 38 References......Page 39 Part II: Examples......Page 42 4.1 Introduction......Page 43 4.2 Motivation and Insight......Page 47 4.2.1 Daubechies 9/7-Tap Bi-orthogonal Filter......Page 48 4.2.2 Le Gall's 5/3 Filter......Page 49 4.3 Background and Related Work......Page 50 4.3.1 Wavelet Transform Background......Page 51 4.3.2 Hardware Implementation of DWT......Page 52 4.4.1 Parameterized Filter Design......Page 53 4.4.2 Numerical Study......Page 54 4.4.3 Candidate Filters......Page 55 4.4.4 Hardware Architectures......Page 57 4.5 Fixed Point Implementation......Page 61 4.6.1 `On-the-Fly' Switching......Page 62 4.6.2 `Bit-Width' Switching......Page 64 4.7.1 Image Reconstruction Quality......Page 65 4.7.2 Hardware vs. Software Performance......Page 66 4.7.3 Hardware Comparison......Page 67 4.7.3.1 ASIC Synthesis......Page 69 4.7.5 Real-World Application......Page 70 References......Page 72 5.1 Introduction......Page 76 5.2 Preliminaries......Page 78 5.2.1 Parameterized Construction of DWT......Page 79 5.2.1.1 Binary Coefficients......Page 80 5.2.1.3 Feasible Range of Parameter alpha......Page 81 5.2.1.4 Key Space......Page 82 5.2.2 Subband Re-orientation......Page 83 5.2.2.3 Key Space......Page 84 5.3 Security......Page 85 5.4 Hardware Implementation......Page 88 5.4.1 Reconfigurable Constant Multiplier (RCM)......Page 89 5.4.1.1 4x4 Bits Multiplier Using LUTs......Page 91 5.4.1.2 Mapping a Generic RCM into LUTs......Page 92 5.5 Parameterized Lifting......Page 93 References......Page 96 6.1.1 Chaos and Cryptography......Page 99 6.1.2 Wavelets and Chaotic Filter Banks......Page 100 6.1.4 Reconfigurable Hardware Implementation of DWT......Page 101 6.2 Chaotic Filter Bank Scheme......Page 102 6.2.2 Key Space......Page 103 6.3 The MCFB Scheme......Page 104 6.4.1 The Modified Logistic Map (MLM)......Page 106 6.6 Resistance of Chaotic Generator Against Cryptanalysis......Page 108 6.6.1.3 Runs Test......Page 109 6.6.1.4 Statistical Properties......Page 110 6.6.3 Lyapunov Exponent......Page 111 6.7 Security Enhancement......Page 113 6.8 Hardware Implementation......Page 114 6.8.1 Hardware Optimizations for ICO......Page 116 References......Page 117 7.1 Introduction......Page 120 7.1.1 Weakness of SAC Coder......Page 121 7.2 Arithmetic Coding with Piece-wise Linear Chaotic Maps......Page 122 7.2.1 Compression Efficiency......Page 124 7.2.2 Binary Chaotic Arithmetic Coding (BCAC)......Page 125 7.3.1 Application to Multimedia/Data Encryption......Page 128 7.3.3 Security Enhancements (SE)......Page 129 7.3.3.2 Key and Output Mixing (MIX) Mode......Page 130 7.3.4 Resistance to Known Attacks......Page 132 7.3.6 Key and Plaintext Sensitivity......Page 134 7.4 Compression......Page 136 7.5 Hardware Implementation......Page 137 7.5.1 Literature Review......Page 138 7.5.2 Implementation Details......Page 139 7.5.4 Binary Chaotic Arithmetic Coder and Encryption (BCAC) Architecture......Page 140 7.5.6 N-ary Chaotic Arithmetic Coder and Encryption (NCAC) Coding......Page 141 7.5.7 Multiple Symbol per Cycle Arithmetic Coding......Page 143 7.6.1 Multiple Huffman Tables......Page 144 7.6.2 Randomized Arithmetic Coding......Page 145 7.6.3 Secure Arithmetic Coding......Page 146 References......Page 147 Chapter 8: Conclusion......Page 150 Index......Page 151