TSV 3D RF Integration: High Resistivity Si Interposer Technology

Description

TSV 3D RF Integration: High Resistivity Si Interposer Technology systematically introduces the design, process development and application verification of high-resistivity silicon interpose technology, addressing issues of high frequency loss and high integration level. The book includes a detailed demonstration of the design and process development of Hr-Si interposer technology, gives case studies, and presents a systematic literature review. Users will find this to be a resource with detailed demonstrations of the design and process development of HR-Si interposer technologies, including quality monitoring and methods to extract S parameters. A series of cases are presented, including an example of an integrated inductor, a microstrip inter-digital filter, and a stacked patch antenna. Each chapter includes a systematic and comparative review of the research literature, offering researchers and engineers in microelectronics a uniquely useful handbook to help solve problems in 3D heterogenous RF integration oriented Hr-Si interposer technology. Front Cover TSV 3D RF Integration: High Resistivity Si Interposer Technology Copyright Contents About the authors Preface by Yufeng Jin Preface by Shenglin Ma Acknowledgments Chapter 1: Introduction to HR-Si interposer technology 1.1. Background 1.2. 3D RF heterogeneous integration scheme 1.3. HR-Si interposer technology 1.4. TGV interposer technology 1.5. Summary 1.6. Main work of this book References Chapter 2: Design, process, and electrical verification of HR-Si interposer for 3D heterogeneous RF integration 2.1. Introduction 2.2. Design and fabrication process of HR-Si TSV interposer 2.3. Design and analysis of RF transmission structure built on HR-Si TSV interposer 2.4. Research on HR-Si TSV interposer fabrication process 2.4.1. Double-sided deep reactive ion etching (DRIE) to open HR-Si TSV 2.4.2. Thermal oxidation to form firm insulation layer 2.4.3. Patterned Cu electroplating to achieve metallization and establish RDL layer 2.4.4. Electroless nickel electroless palladium immersion gold (ENEPIG) 2.4.5. Surface passivation 2.5. Electrical characteristics analysis of transmission structure on HR-Si TSV interposer 2.6. Conclusion References Chapter 3: Design, verification, and optimization of novel 3D RF TSV based on HR-Si interposer 3.1. Introduction 3.2. HR-Si TSV-based coaxial-like transmission structure 3.3. Redundant RF TSV transmission structure 3.4. Sample processing and test result analysis 3.5. Optimization of HR-Si TSV interposer 3.6. Conclusion References Chapter 4: HR-Si TSV integrated inductor 4.1. Introduction 4.2. HR-Si TSV interposer integrated planar inductor 4.3. Research on 3D inductor based on HR-Si interposer 4.4. Summary References Chapter 5: Verification of 2.5D/3D heterogeneous RF integration of HR-Si interposer 5.1. Introduction 5.2. Four-channel 2.5D heterogeneous integrated L-band receiver 5.3. 3D heterogeneous integrated channelized frequency conversion receiver based on HR-Si interposer 5.3.1. HR-Si interposer integrated microstrip interdigital filter 5.3.2. Design, fabrication, and test of HR-Si interposer 5.3.3. 3D heterogeneous integrated assembly and test 5.4. Conclusions References Chapter 6: HR-Si interposer embedded microchannel 6.1. Introduction 6.2. Design of a HR-Si interposer embedded microchannel 6.3. Thermal characteristics analysis of a TSV interposer embedded microchannel 6.3.1. Simplified calculation based on a variable diffusion angle 6.3.2. Direct calculation based on analytical formula 6.3.3. A fitting formula based on simulation results 6.3.4. Equivalent thermal resistance network based on the high thermal conductivity path 6.4. Process development of a TSV interposer embedded microchannel 6.5. Characterization of cooling capacity of HR-Si interposer with an embedded microchannel 6.6. Evaluation of HR-Si interposer embedded with a cooling microchannel 6.7. Application verification of HR-Si interposer embedded with microchannel 6.8. Conclusions References Chapter 7: Patch antenna in stacked HR-Si interposers 7.1. Introduction 7.2. Theoretical basis of patch antenna 7.3. Design of a patch antenna in stacked HR-Si interposers 7.4. Processing of a patch antenna in stacked HR-Si interposers 7.5. Test and analysis of patch antenna in stacked HR-Si TSV interposer 7.6. Summary References Chapter 8: Through glass via technology 8.1. Introduction 8.2. TGV fabrication 8.3. Metallization of TGV 8.4. Passive devices based on TGV technology 8.4.1. Technology description 8.4.2. MIM capacitor 8.4.3. TGV-based bandpass filter 8.5. Embedded glass fan-out wafer-level package technology 8.5.1. Technology description 8.5.2. AIP enabled by eGFO package technology 8.5.3. 3D RF integration enabled by eGFO package technology 8.6. 2.5D heterogeneous integrated L-band receiver based on TGV interposer 8.7. Conclusions References Chapter 9: Conclusion and outlook Appendix 1 : Abbreviations Appendix 2 : Nomenclature Appendix 3 : Conversion factors Index Back Cover