VLSI Architectures for Future Video Coding (Materials, Circuits and Devices)

Description

This book addresses future video coding from the perspective of hardware implementation and architecture design, with particular focus on approximate computing and the energy-quality scalability paradigm. Challenges in deploying VLSI architectures for video coding are identified and potential solutions postulated with reference to recent research in the field. The book offers systematic coverage of the designs, techniques and paradigms that will most likely be exploited in the design of VLSI architectures for future video coding systems. Written by a team of expert authors from around the world, and brought together by an editor who is a recognised authority in the field, this book is a useful resource for academics and industry professionals working on VLSI implementation of video codecs. Cover Contents Preface 1 Scalable transform architectures for video coding 1.1 Introduction 1.2 Review of scalable transforms in HEVC 1.2.1 Transform coding in HEVC 1.2.2 Approximate DCT algorithms and their hardware architecture for HEVC 1.2.2.1 Recursive sparse matrix decomposition 1.2.2.2 Sparse matrix decomposition based on a new 4-point DCT approximation 1.2.3 Complexity analysis 1.2.4 Synthesis results 1.3 Video-coding concept in VVC standard 1.3.1 VVC encoder scheme 1.3.2 Transform coding for VVC standard 1.3.3 Statistical analysis 1.4 Approximation for DCT-II transform and its hardware architecture 1.4.1 Algorithm description 1.4.2 Approximate 8-point transform architecture 1.4.3 Reconfigurable designs for 1D/2D DCT computing 1.4.3.1 Reconfigurable design for 4-and 8-point 1D DCT computing 1.4.3.2 Reconfigurable design for 32-point 1D DCT computing 1.4.3.3 Reconfigurable architecture for 2D approximate DCT computing 1.4.3.4 Reconfigurable architecture for inverse and forward DCT computing 1.4.4 Video-coding performance 1.4.4.1 Simulation conditions 1.4.4.2 Evaluation criteria 1.4.4.3 Results and discussions 1.4.4.4 RD curves 1.5 New approximation for DST-VII transform 1.5.1 Algorithm description 1.5.2 Video-coding performance 1.6 Conclusion References 2 Joint algorithm-architecture design of video coding modules 2.1 Introduction 2.2 Video coding evolution and state of the art 2.2.1 Evolution of video coding standards 2.2.2 Overview of HEVC and VVC codecs 2.3 Video coding application analysis 2.3.1 Analysis of VVC and HEVC encoders 2.3.1.1 Compression efficiency 2.3.1.2 Computational effort 2.4 Rate – distortion optimization 2.4.1 Block-partitioning decisions 2.4.2 Distortion metrics 2.4.2.1 Sum of absolute differences 2.4.2.2 Sum of absolute transformed differences 2.4.3 Challenges on rate–distortion optimization for VVC encoder 2.5 Inter-frame prediction 2.5.1 Integer motion estimation 2.5.2 Fractional motion estimation 2.5.3 Dedicated memories for motion estimation 2.6 Intra-frame prediction 2.6.1 Intra-prediction mode decision in H. 265/HEVC 2.6.2 Hardware architecture for the HEVC intra-prediction 2.6.3 Challenges on intra-frame prediction architecture design for VVC encoder 2.7 Transforms 2.7.1 Challenges of transforms architecture design for VVC encoder 2.8 In-loop filter 2.9 Entropy coding 2.9.1 Upcoming challenges related to entropy encoding 2.10 Conclusions Acknowledgements References 3 High-throughput architectures for high-resolution video coding: system architecture analysis 3.1 Hardware vs. software encoders 3.2 Hardware optimization techniques 3.3 Timing constraints on pixel units 3.4 Mode decision tradeoffs 3.4.1 Reconstruction loop 3.4.2 Transforms 3.4.3 Mode preselection 3.4.4 Cost estimation 3.5 Motion estimation and compensation 3.5.1 Search strategy 3.5.2 Fractional-pel motion estimation 3.5.3 Access to memories 3.5.4 Motion vector prediction 3.6 Entropy coding 3.7 Summary References 4 High-throughput architectures for highresolution video coding: hardwired oriented algorithms and VLSI architectures 4.1 Reconstruction loop 4.1.1 Transform architectures 4.1.2 Parallel loops 4.1.3 Interleaved processing order 4.2 Rate – distortion optimization 4.2.1 RDO based on signal features 4.2.2 Simplified rate estimation 4.2.3 Simplified distortion estimation 4.3 Intra mode decision 4.4 Motion estimation 4.4.1 Full search 4.4.2 Hierarchical search 4.4.3 Test zone search 4.5 Entropy coder 4.6 Summary References 5 Low-power circuit design techniques for high-resolution video coding 5.1 Introduction 5.2 Power dissipation in CMOS and a methodology estimation using real-video data 5.2.1 Sources of power dissipation 5.2.1.1 Static power 5.2.1.2 Short-circuit power 5.2.1.3 Switching power (dynamic power) 5.2.2 Power estimation in the current industrial ASIC design flow 5.3 Compute-intensive video-coding blocks overview 5.3.1 Sum of absolute differences 5.3.2 Sum of absolute transformed differences 5.3.3 Interpolation filter 5.4 Low-power design techniques 5.4.1 Compression-based operators 5.4.1.1 Internal structures of adder compressors 5.4.1.2 Hierarchical adder compressors 5.4.2 Hybrid encoding 5.4.2.1 Hybrid code definition 5.4.2.2 Hybrid adder 5.4.3 Approximate computing using pruning for SATD 5.4.3.1 Pruning-based algorithm 5.5 Low-power techniques for video-coding blocks—applications and results 5.5.1 SAD block with adders compressors and hybrid adder 5.5.1.1 SAD with adders compressors 5.5.1.2 SAD with hybrid adder 5.5.2 SATD architecture with pruning 5.5.2.1 Results and discussions of the SATD pruning techniques 5.5.3 Interpolation filter with adder compressors 5.5.3.1 Interpolation filters architecture using adder compressors 5.5.3.2 Interpolation filter architecture results 5.6 Conclusions References 6 Real-time architectures for 3D video coding 6.1 3D-high efficiency video coding: a 3D-video-coding standard supporting the multiview plus depth format 6.1.1 Memory, processing, and complexity challenges on 3D-HEVC intra-prediction 6.1.2 Memory, processing, and complexity challenges on 3D-HEVC inter-frame and inter-view predictions 6.2 3D-HEVC real-time architecture for DMM-1 and DMM-4 intra-frame prediction modes 6.2.1 DMM-1 algorithm simplification 6.2.2 Bipartition modes architecture 6.2.3 Synthesis results 6.3 3D-HEVC real-time architecture for DIS intra-frame prediction mode 6.3.1 Depth intra skip algorithm simplification 6.3.2 Depth intra skip architecture 6.3.3 Synthesis results 6.4 3D-HEVC real-time architecture for inter-frame and inter-view predictions 6.4.1 The energy-aware motion and disparity estimation system 6.4.2 Proposed hardware-oriented algorithms 6.4.3 The on-chip memory design and management based on channel aspects 6.4.4 Hardware results 6.5 Conclusions Acknowledgements References 7 Frame memory compression for high-resolution video coding 7.1 Prediction 7.1.1 Differential pulse-code modulation 7.1.2 Intra-mode referenced in-block prediction 7.1.3 Block truncation coding 7.1.4 Hierarchical minimum and difference 7.1.5 Hierarchical average and copy 7.1.6 Modified Hadamard transform 7.1.7 Discrete cosine transform 7.2 Entropy coding 7.2.1 Coding methods in frame compression 7.2.2 Huffman coding 7.2.3 Golomb coding 7.2.4 SFL coding and SBT coding 7.3 Memory organization 7.3.1 Works on bandwidth efficiency 7.3.1.1 Address table compression and reference memory access style of IP module and ME module 7.3.1.2 Pixels duplication and luma–chroma correlated mapping 7.3.1.3 TLB addressing and fixed addressing 7.3.1.4 Dual-mode memory addressing (DMMA): direct block memory access (DBMA) and relative block memory access (RBMA) 7.3.2 Works on power consumption 7.3.2.1 Different-level memory mapping for VCR-LFRC (variable-compression-ratio lossless frame recompression) 7.3.2.2 Main memory and auxiliary memory 7.3.2.3 Partition group table-based compression storage 7.3.3 Other works 7.3.3.1 MB-column-based memory mapping References 8 Discrete transform approximations for video coding 8.1 Introduction 8.2 Literature review 8.3 Design of approximate transforms 8.3.1 Design parameters 8.3.2 Scalable transforms 8.4 Evaluation metrics 8.4.1 The weighted total error energy 8.4.2 The weighted mean square error 8.4.3 The unified transform coding gain 8.4.4 The transform efficiency 8.4.5 Specification of the weighting matrix W 8.5 Efficient transforms 8.5.1 Multicriteria optimization 8.5.2 Efficient solutions 8.6 Video coding experiments 8.7 Hardware implementation 8.8 Conclusions Acknowledgements References 9 Reconfigurable and approximate computing for video coding 9.1 Constraints and needs of video-coding systems 9.1.1 Chapter organization 9.2 Reconfigurable video coding 9.2.1 Overview of the standard and its features 9.2.2 Dynamic reconfiguration exploiting MPEG-RVC 9.2.3 MPEG-RVC key remarks 9.3 Approximate video-coding systems 9.3.1 Data-level approximation 9.3.2 Hardware level approximation 9.3.3 Computation level approximation 9.3.4 Approximate computing key remarks 9.4 Final remarks Acknowledgment References 10 Future video coding: new tools and algorithms 10.1 Context and international bodies 10.2 Video coding 10.2.1 Video-coding chain 10.2.1.1 Source acquisition 10.2.1.2 Preprocessing 10.2.1.3 Encoding 10.2.1.4 Transmission 10.2.1.5 Decoding 10.2.1.6 Post-processing 10.2.1.7 Display 10.3 Inside a video 10.4 Representation of color 10.4.1 Fundamentals of radiometry and photometry 10.4.2 Human-visual system 10.4.3 Color space CIE 1931 XYZ 10.5 State of the art of audio–video technologies 10.5.1 High dynamic range 10.5.2 Wide color gamut 10.5.3 Transfer functions: EOTF and OETF 10.5.4 Perceptual quantizer 10.5.5 Hybrid log-gamma 10.5.6 Other HDR formats 10.5.7 High frame rate 10.6 Hybrid video-coding scheme 10.6.1 Picture partitioning 10.6.2 Intra-prediction 10.6.3 Inter-prediction 10.7 Evolution of video services and video-compression technologies and standardization activities in MPEG 10.7.1 Description of the VVC coding tools 10.7.1.1 Frame partitioning 10.7.1.2 Intra-prediction 10.7.1.3 Inter-prediction 10.7.1.4 Transform improvements 10.7.1.5 Loop filter 10.7.1.6 Entropy coding 10.8 The codec battle References Index Back Cover