VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms: 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8–10, 2018, Revised and Extended Selected Papers

Description

This book contains extended and revised versions of the best papers presented at the 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, held in Verona, Italy, in October 2018. The 13 full papers included in this volume were carefully reviewed and selected from the 27 papers (out of 106 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like heterogeneous, neuromorphic and brain-inspired, biologically-inspired, approximate computing systems. Front Matter ....Pages i-xiv A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load (Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada)....Pages 1-13 An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication (Shahzad Muzaffar, Ibrahim (Abe) M. Elfadel)....Pages 14-31 The Connection Layout in a Lattice of Four-Terminal Switches (Anna Bernasconi, Antonio Boffa, Fabrizio Luccio, Linda Pagli)....Pages 32-52 Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS (L. Stornaiuolo, M. Rabozzi, M. D. Santambrogio, D. Sciuto, C. B. Ciobanu, G. Stramondo et al.)....Pages 53-78 Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields (Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu)....Pages 79-106 Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis (Valentino Peluso, Andrea Calimera)....Pages 107-127 ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code (Swagata Mandal, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay)....Pages 128-146 Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems (Md Adnan Zaman, Rajeev Joshi, Srinivas Katkoori)....Pages 147-166 Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis (Francesco Barchi, Gianvito Urgese, Enrico Macii, Andrea Acquaviva)....Pages 167-186 Improved Test Solutions for COTS-Based Systems in Space Applications (Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sanchez, Matteo Sonza Reorda, Jan-Gerd Mess)....Pages 187-206 Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection (Victor Champac, Andres Gomez, Freddy Forero, Kaushik Roy)....Pages 207-231 Assessment of Low-Budget Targeted Cyberattacks Against Power Systems (XiaoRui Liu, Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos)....Pages 232-256 Efficient Hardware/Software Co-design for NTRU (Tim Fritzmann, Thomas Schamberger, Christoph Frisch, Konstantin Braun, Georg Maringer, Johanna Sepúlveda)....Pages 257-280 Correction to: Improved Test Solutions for COTS-Based Systems in Space Applications (Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sanchez, Matteo Sonza Reorda, Jan-Gerd Mess)....Pages C1-C1 Back Matter ....Pages 281-281