PCI Express 6.0 Specification

Description

PCI Express® Base Specification Revision 6.0 Front Matter Table of Contents List of Figures List of Equations List of Tables Status of this Document Revision History Objective of the PCI Express® Architecture PCI Express Architecture Specification Organization Documentation Conventions Terms and Acronyms Reference Documents Chapter 1. Introduction Section 1.1 An Evolving I/O Interconnect Section 1.2 PCI Express Link Section 1.3 PCI Express Fabric Topology Section 1.3.1 Root Complex Section 1.3.2 Endpoints Section 1.3.2.1 Legacy Endpoint Rules Section 1.3.2.2 PCI Express Endpoint Rules Section 1.3.2.3 Root Complex Integrated Endpoint Rules Section 1.3.3 Switch Section 1.3.4 Root Complex Event Collector Section 1.3.5 PCI Express to PCI/PCI-X Bridge Section 1.4 Hardware/Software Model for Discovery, Configuration and Operation Section 1.5 PCI Express Layering Overview Section 1.5.1 Transaction Layer Section 1.5.2 Data Link Layer Section 1.5.3 Physical Layer Section 1.5.4 Layer Functions and Services Section 1.5.4.1 Transaction Layer Services Section 1.5.4.2 Data Link Layer Services Section 1.5.4.3 Physical Layer Services Section 1.5.4.4 Inter-Layer Interfaces Section 1.5.4.4.1 Transaction/Data Link Interface Section 1.5.4.4.2 Data Link/Physical Interface Chapter 2. Transaction Layer Specification Section 2.1 Transaction Layer Overview Section 2.1.1 Address Spaces, Transaction Types, and Usage Section 2.1.1.1 Memory Transactions Section 2.1.1.2 I/O Transactions Section 2.1.1.3 Configuration Transactions Section 2.1.1.4 Message Transactions Section 2.1.2 Packet Format Overview Section 2.2 Transaction Layer Protocol - Packet Definition Section 2.2.1 Common Packet Header Fields Section 2.2.1.1 Common Packet Header Fields for Non-Flit Mode Section 2.2.1.2 Common Packet Header Fields for Flit Mode Section 2.2.2 TLPs with Data Payloads - Rules Section 2.2.3 TLP Digest Rules - Non-Flit Mode Only Section 2.2.4 Routing and Addressing Rules Section 2.2.4.1 Address-Based Routing Rules Section 2.2.4.2 ID Based Routing Rules Section 2.2.5 First/Last DW Byte Enables Rules Section 2.2.5.1 Byte Enable Rules for Non-Flit Mode Section 2.2.5.2 Byte Enable Rules for Flit Mode Section 2.2.6 Transaction Descriptor Section 2.2.6.1 Overview Section 2.2.6.2 Transaction Descriptor - Transaction ID Field Section 2.2.6.3 Transaction Descriptor - Attributes Field Section 2.2.6.4 Relaxed Ordering and ID-Based Ordering Attributes Section 2.2.6.5 No Snoop Attribute Section 2.2.6.6 Transaction Descriptor - Traffic Class Field Section 2.2.7 Memory, I/O, and Configuration Request Rules Section 2.2.7.1 Non-Flit Mode Section 2.2.7.1.1 TPH Rules Section 2.2.7.2 Flit Mode Section 2.2.8 Message Request Rules Section 2.2.8.1 INTx Interrupt Signaling - Rules Section 2.2.8.2 Power Management Messages Section 2.2.8.3 Error Signaling Messages Section 2.2.8.4 Locked Transactions Support Section 2.2.8.5 Slot Power Limit Support Section 2.2.8.6 Vendor_Defined Messages Section 2.2.8.6.1 PCI-SIG Defined VDMs Section 2.2.8.6.2 Device Readiness Status (DRS) Message Section 2.2.8.6.3 Function Readiness Status Message (FRS Message) Section 2.2.8.6.4 Hierarchy ID Message Section 2.2.8.7 Ignored Messages Section 2.2.8.8 Latency Tolerance Reporting (LTR) Message Section 2.2.8.9 Optimized Buffer Flush/Fill (OBFF) Message Section 2.2.8.10 Precision Time Measurement (PTM) Messages Section 2.2.8.11 Integrity and Data Encryption (IDE) Messages Section 2.2.9 Completion Rules Section 2.2.9.1 Completion Rules for Non-Flit Mode Section 2.2.9.2 Completion Rules for Flit Mode Section 2.2.10 TLP Prefix Rules Section 2.2.10.1 TLP Prefix General Rules - Non-Flit Mode Section 2.2.10.2 Local TLP Prefix Processing Section 2.2.10.2.1 Vendor Defined Local TLP Prefix Section 2.2.10.3 Flit Mode Local TLP Prefix Section 2.2.10.4 End-End TLP Prefix Processing - Non-Flit Mode Section 2.2.10.4.1 Vendor Defined End-End TLP Prefix Section 2.2.10.4.2 Root Ports with End-End TLP Prefix Supported Section 2.2.11 OHC-E Rules - Flit Mode Section 2.3 Handling of Received TLPs Section 2.3.1 Request Handling Rules Section 2.3.1.1 Data Return for Read Requests Section 2.3.2 Completion Handling Rules Section 2.4 Transaction Ordering Section 2.4.1 Transaction Ordering Rules Section 2.4.2 Update Ordering and Granularity Observed by a Read Transaction Section 2.4.3 Update Ordering and Granularity Provided by a Write Transaction Section 2.5 Virtual Channel (VC) Mechanism Section 2.5.1 Virtual Channel Identification (VC ID) Section 2.5.2 TC to VC Mapping Section 2.5.3 VC and TC Rules Section 2.6 Ordering and Receive Buffer Flow Control Section 2.6.1 Flow Control (FC) Rules Section 2.6.1.1 FC Information Tracked by Transmitter Section 2.6.1.2 FC Information Tracked by Receiver Section 2.7 End-to-End Data Integrity Section 2.7.1 ECRC Rules Section 2.7.2 Error Forwarding (Data Poisoning) Section 2.7.2.1 Rules For Use of Data Poisoning Section 2.8 Completion Timeout Mechanism Section 2.9 Link Status Dependencies Section 2.9.1 Transaction Layer Behavior in DL_Down Status Section 2.9.2 Transaction Layer Behavior in DL_Up Status Section 2.9.3 Transaction Layer Behavior During Downstream Port Containment Chapter 3. Data Link Layer Specification Section 3.1 Data Link Layer Overview Section 3.2 Data Link Control and Management State Machine Section 3.2.1 Data Link Control and Management State Machine Rules Section 3.3 Data Link Feature Exchange Section 3.4 Flow Control Initialization Protocol Section 3.4.1 Flow Control Initialization State Machine Rules Section 3.4.2 Scaled Flow Control Section 3.5 Data Link Layer Packets (DLLPs) Section 3.5.1 Data Link Layer Packet Rules Section 3.6 Data Integrity Mechanisms Section 3.6.1 Introduction Section 3.6.2 LCRC, Sequence Number, and Retry Management (TLP Transmitter) Section 3.6.2.1 LCRC and Sequence Number Rules (TLP Transmitter) Section 3.6.2.2 Handling of Received DLLPs (Non-Flit Mode) Section 3.6.2.3 Handling of Received DLLPs (Flit Mode) Section 3.6.3 LCRC and Sequence Number (TLP Receiver) (Non-Flit Mode) Section 3.6.3.1 LCRC and Sequence Number Rules (TLP Receiver) Chapter 4. Physical Layer Logical Block Section 4.1 Introduction Section 4.2 Logical Sub-block Section 4.2.1 8b/10b Encoding for 2.5 GT/s and 5.0 GT/s Data Rates Section 4.2.1.1 Symbol Encoding Section 4.2.1.1.1 Serialization and De-serialization of Data Section 4.2.1.1.2 Special Symbols for Framing and Link Management (K Codes) Section 4.2.1.1.3 8b/10b Decode Rules Section 4.2.1.2 Framing and Application of Symbols to Lanes Section 4.2.1.2.1 Framing and Application of Symbols to Lanes for TLPs and DLLPs in Non-Flit Mode Section 4.2.1.3 Data Scrambling Section 4.2.2 128b/130b Encoding for 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s Data Rates Section 4.2.2.1 Lane Level Encoding Section 4.2.2.2 Ordered Set Blocks Section 4.2.2.2.1 Block Alignment Section 4.2.2.3 Data Blocks Section 4.2.2.3.1 Framing Tokens in Non-Flit-Mode Section 4.2.2.3.2 Transmitter Framing Requirements in Non-Flit Mode Section 4.2.2.3.3 Receiver Framing Requirements in Non-Flit Mode Section 4.2.2.3.4 Receiver Framing Requirements in Flit Mode Section 4.2.2.3.5 Recovery from Framing Errors in Non-Flit Mode and Flit Mode Section 4.2.2.4 Scrambling in Non-Flit Mode and Flit Mode Section 4.2.2.5 Precoding Section 4.2.2.5.1 Precoding at 32.0 GT/s Data Rate Section 4.2.2.6 Loopback with 128b/130b Code in Non-Flit Mode and Flit Mode Section 4.2.3 Flit Mode Operation Section 4.2.3.1 1b/1b Encoding for 64.0 GT/s and higher Data Rates Section 4.2.3.1.1 PAM4 Signaling Section 4.2.3.1.2 1b/1b Scrambling Section 4.2.3.1.3 Gray Coding at 64.0 GT/s and Higher Data Rates Section 4.2.3.1.4 Precoding at 64.0 GT/s and Higher Data Rates Section 4.2.3.1.5 Ordered Set Blocks at 64.0 GT/s and Higher Data Rates Section 4.2.3.1.6 Alignment at Block/ Flit Level for 1b/1b Encoding Section 4.2.3.2 Processing of Ordered Sets During Flit Mode Data Stream Section 4.2.3.3 Data Stream in Flit Mode Section 4.2.3.4 Bytes in Flit Layout Section 4.2.3.4.1 TLP Bytes in Flit Section 4.2.3.4.2 DLP Bytes in Flit Section 4.2.3.4.2.1 Flit Sequence Number and Retry Mechanism Section 4.2.3.4.2.1.1 IDLE Flit Handshake Phase Section 4.2.3.4.2.1.2 Sequence Number Handshake Phase Section 4.2.3.4.2.1.3 Normal Flit Exchange Phase Section 4.2.3.4.2.1.4 Received Ack and Nak Processing Section 4.2.3.4.2.1.5 Ack, Nak, and Discard Rules Section 4.2.3.4.2.1.6 Flit Replay Scheduling Section 4.2.3.4.2.1.7 Flit Replay Transmit Rules Section 4.2.3.4.3 CRC Bytes in Flit Section 4.2.3.4.4 ECC Bytes in Flit Section 4.2.3.4.5 Ordered Set insertion in Data Stream in Flit Mode Section 4.2.4 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates Section 4.2.4.1 Rules for Transmitter Coefficients Section 4.2.4.2 Encoding of Presets Section 4.2.5 Link Initialization and Training Section 4.2.5.1 Training Sequences Section 4.2.5.2 Alternate Protocol Negotiation Section 4.2.5.3 Electrical Idle Sequences (EIOS and EIEOS) Section 4.2.5.4 Inferring Electrical Idle Section 4.2.5.5 Lane Polarity Inversion Section 4.2.5.6 Fast Training Sequence (FTS) Section 4.2.5.7 Start of Data Stream Ordered Set (SDS Ordered Set) Section 4.2.5.8 Link Error Recovery Section 4.2.5.9 Reset Section 4.2.5.9.1 Fundamental Reset Section 4.2.5.9.2 Hot Reset Section 4.2.5.10 Link Data Rate Negotiation Section 4.2.5.11 Link Width and Lane Sequence Negotiation Section 4.2.5.11.1 Required and Optional Port Behavior Section 4.2.5.12 Lane-to-Lane De-skew Section 4.2.5.13 Lane vs. Link Training Section 4.2.6 Link Training and Status State Machine (LTSSM) Descriptions Section 4.2.6.1 Detect Overview Section 4.2.6.2 Polling Overview Section 4.2.6.3 Configuration Overview Section 4.2.6.4 Recovery Overview Section 4.2.6.5 L0 Overview Section 4.2.6.6 L0s Overview Section 4.2.6.7 L0p Overview Section 4.2.6.7.1 Link Management DLLP Section 4.2.6.8 L1 Overview Section 4.2.6.9 L2 Overview Section 4.2.6.10 Disabled Overview Section 4.2.6.11 Loopback Overview Section 4.2.6.12 Hot Reset Overview Section 4.2.7 Link Training and Status State Rules Section 4.2.7.1 Detect Section 4.2.7.1.1 Detect.Quiet Section 4.2.7.1.2 Detect.Active Section 4.2.7.2 Polling Section 4.2.7.2.1 Polling.Active Section 4.2.7.2.2 Polling.Compliance Section 4.2.7.2.3 Polling.Configuration Section 4.2.7.2.4 Polling.Speed Section 4.2.7.3 Configuration Section 4.2.7.3.1 Configuration.Linkwidth.Start Section 4.2.7.3.1.1 Downstream Lanes Section 4.2.7.3.1.2 Upstream Lanes Section 4.2.7.3.2 Configuration.Linkwidth.Accept Section 4.2.7.3.2.1 Downstream Lanes Section 4.2.7.3.2.2 Upstream Lanes Section 4.2.7.3.3 Configuration.Lanenum.Accept Section 4.2.7.3.3.1 Downstream Lanes Section 4.2.7.3.3.2 Upstream Lanes Section 4.2.7.3.4 Configuration.Lanenum.Wait Section 4.2.7.3.4.1 Downstream Lanes Section 4.2.7.3.4.2 Upstream Lanes Section 4.2.7.3.5 Configuration.Complete Section 4.2.7.3.5.1 Downstream Lanes Section 4.2.7.3.5.2 Upstream Lanes Section 4.2.7.3.6 Configuration.Idle Section 4.2.7.4 Recovery Section 4.2.7.4.1 Recovery.RcvrLock Section 4.2.7.4.2 Recovery.Equalization Section 4.2.7.4.2.1 Downstream Lanes Section 4.2.7.4.2.1.1 Phase 1 of Transmitter Equalization Section 4.2.7.4.2.1.2 Phase 2 of Transmitter Equalization Section 4.2.7.4.2.1.3 Phase 3 of Transmitter Equalization Section 4.2.7.4.2.2 Upstream Lanes Section 4.2.7.4.2.2.1 Phase 0 of Transmitter Equalization Section 4.2.7.4.2.2.2 Phase 1 of Transmitter Equalization Section 4.2.7.4.2.2.3 Phase 2 of Transmitter Equalization Section 4.2.7.4.2.2.4 Phase 3 of Transmitter Equalization Section 4.2.7.4.3 Recovery.Speed Section 4.2.7.4.4 Recovery.RcvrCfg Section 4.2.7.4.5 Recovery.Idle Section 4.2.7.5 L0 Section 4.2.7.6 L0s Section 4.2.7.6.1 Receiver L0s Section 4.2.7.6.1.1 Rx_L0s.Entry Section 4.2.7.6.1.2 Rx_L0s.Idle Section 4.2.7.6.1.3 Rx_L0s.FTS Section 4.2.7.6.2 Transmitter L0s Section 4.2.7.6.2.1 Tx_L0s.Entry Section 4.2.7.6.2.2 Tx_L0s.Idle Section 4.2.7.6.2.3 Tx_L0s.FTS Section 4.2.7.7 L1 Section 4.2.7.7.1 L1.Entry Section 4.2.7.7.2 L1.Idle Section 4.2.7.8 L2 Section 4.2.7.8.1 L2.Idle Section 4.2.7.8.2 L2.TransmitWake Section 4.2.7.9 Disabled Section 4.2.7.10 Loopback Section 4.2.7.10.1 Loopback.Entry Section 4.2.7.10.2 Loopback.Active Section 4.2.7.10.3 Loopback.Exit Section 4.2.7.11 Hot Reset Section 4.2.8 Clock Tolerance Compensation Section 4.2.8.1 SKP Ordered Set for 8b/10b Encoding Section 4.2.8.2 SKP Ordered Set for 128b/130b Encoding Section 4.2.8.3 SKP Ordered Set for 1b/1b Encoding Section 4.2.8.4 Rules for Transmitters Section 4.2.8.5 Rules for Receivers Section 4.2.9 Compliance Pattern in 8b/10b Encoding Section 4.2.10 Modified Compliance Pattern in 8b/10b Encoding Section 4.2.11 Compliance Pattern in 128b/130b Encoding Section 4.2.12 Modified Compliance Pattern in 128b/130b Encoding Section 4.2.13 Jitter Measurement Pattern in 128b/130b Section 4.2.14 Compliance Pattern in 1b/1b Encoding Section 4.2.15 Modified Compliance Pattern in 1b/1b Encoding Section 4.2.16 Jitter Measurement Pattern in 1b/1b Encoding Section 4.2.17 Toggle Patterns in 1b/1b encoding Section 4.2.18 Lane Margining at Receiver Section 4.2.18.1 Receiver Number, Margin Type, Usage Model, and Margin Payload Fields Section 4.2.18.1.1 Step Margin Execution Status Section 4.2.18.1.2 Margin Payload for Step Margin Commands Section 4.2.18.2 Margin Command and Response Flow Section 4.2.18.3 Receiver Margin Testing Requirements Section 4.3 Retimers Section 4.3.1 Retimer Requirements Section 4.3.2 Supported Retimer Topologies Section 4.3.3 Variables Section 4.3.4 Receiver Impedance Propagation Rules Section 4.3.5 Switching Between Modes Section 4.3.6 Forwarding Rules Section 4.3.6.1 Forwarding Type Rules Section 4.3.6.2 Orientation, Lane Numbers, and Data Stream Mode Rules Section 4.3.6.3 Electrical Idle Exit Rules Section 4.3.6.4 Data Rate Change and Determination Rules Section 4.3.6.5 Electrical Idle Entry Rules Section 4.3.6.6 Transmitter Settings Determination Rules Section 4.3.6.7 Ordered Set Modification Rules Section 4.3.6.8 DLLP, TLP, Logical Idle, and Flit Modification Rules Section 4.3.6.9 8b/10b Encoding Rules Section 4.3.6.10 8b/10b Scrambling Rules Section 4.3.6.11 Hot Reset Rules Section 4.3.6.12 Disable Link Rules Section 4.3.6.13 Loopback Section 4.3.6.14 Compliance Receive Rules Section 4.3.6.15 Enter Compliance Rules Section 4.3.7 Execution Mode Rules Section 4.3.7.1 CompLoadBoard Rules Section 4.3.7.1.1 CompLoadBoard.Entry Section 4.3.7.1.2 CompLoadBoard.Pattern Section 4.3.7.1.3 CompLoadBoard.Exit Section 4.3.7.2 Link Equalization Rules Section 4.3.7.2.1 Downstream Lanes Section 4.3.7.2.1.1 Phase 1 Section 4.3.7.2.1.2 Phase 2 Section 4.3.7.2.1.3 Phase 3 Active Section 4.3.7.2.1.4 Phase 3 Passive Section 4.3.7.2.2 Upstream Lanes Section 4.3.7.2.2.1 Phase 0 Section 4.3.7.2.2.2 Phase 1 Active Section 4.3.7.2.2.3 Phase 2 Active Section 4.3.7.2.2.4 Phase 2 Passive Section 4.3.7.2.2.5 Phase 3 Section 4.3.7.2.3 Force Timeout Section 4.3.7.3 Follower Loopback Section 4.3.7.3.1 Follower Loopback.Entry Section 4.3.7.3.2 Follower Loopback.Active Section 4.3.7.3.3 Follower Loopback.Exit Section 4.3.8 Retimer Latency Section 4.3.8.1 Measurement Section 4.3.8.2 Maximum Limit on Retimer Latency Section 4.3.8.3 Impacts on Upstream and Downstream Ports Section 4.3.9 SRIS Section 4.3.10 L1 PM Substates Support Section 4.3.11 Retimer Configuration Parameters Section 4.3.11.1 Global Parameters Section 4.3.11.2 Per Physical Pseudo Port Parameters Section 4.3.12 In Band Register Access Chapter 5. Power Management Section 5.1 Overview Section 5.2 Link State Power Management Section 5.3 PCI-PM Software Compatible Mechanisms Section 5.3.1 Device Power Management States (D-States) of a Function Section 5.3.1.1 D0 State Section 5.3.1.2 D1 State Section 5.3.1.3 D2 State Section 5.3.1.4 D3 State Section 5.3.1.4.1 D3Hot State Section 5.3.1.4.2 D3Cold State Section 5.3.2 PM Software Control of the Link Power Management State Section 5.3.2.1 Entry into the L1 State Section 5.3.2.2 Exit from L1 State Section 5.3.2.3 Entry into the L2/L3 Ready State Section 5.3.3 Power Management Event Mechanisms Section 5.3.3.1 Motivation Section 5.3.3.2 Link Wakeup Section 5.3.3.2.1 PME Synchronization Section 5.3.3.3 PM_PME Messages Section 5.3.3.3.1 PM_PME “Backpressure” Deadlock Avoidance Section 5.3.3.4 PME Rules Section 5.3.3.5 PM_PME Delivery State Machine Section 5.4 Native PCI Express Power Management Mechanisms Section 5.4.1 Active State Power Management (ASPM) Section 5.4.1.1 L0s ASPM State Section 5.4.1.1.1 Entry into the L0s State Section 5.4.1.1.2 Exit from the L0s State Section 5.4.1.2 ASPM L0p State Section 5.4.1.3 ASPM L1 State Section 5.4.1.3.1 ASPM Entry into the L1 State Section 5.4.1.3.2 Exit from the L1 State Section 5.4.1.4 ASPM Configuration Section 5.4.1.4.1 Software Flow for Enabling or Disabling ASPM Section 5.5 L1 PM Substates Section 5.5.1 Entry conditions for L1 PM Substates and L1.0 Requirements Section 5.5.2 L1.1 Requirements Section 5.5.2.1 Exit from L1.1 Section 5.5.3 L1.2 Requirements Section 5.5.3.1 L1.2.Entry Section 5.5.3.2 L1.2.Idle Section 5.5.3.3 L1.2.Exit Section 5.5.3.3.1 Exit from L1.2 Section 5.5.4 L1 PM Substates Configuration Section 5.5.5 L1 PM Substates Timing Parameters Section 5.5.6 Link Activation Section 5.6 Auxiliary Power Support Section 5.7 Power Management System Messages and DLLPs Section 5.8 PCI Function Power State Transitions Section 5.9 State Transition Recovery Time Requirements Section 5.10 SR-IOV Power Management Section 5.10.1 VF Device Power Management States Section 5.10.2 PF Device Power Management States Section 5.11 PCI Bridges and Power Management Section 5.11.1 Switches and PCI Express to PCI Bridges Section 5.12 Power Management Events Chapter 6. System Architecture Section 6.1 Interrupt and PME Support Section 6.1.1 Rationale for PCI Express Interrupt Model Section 6.1.2 PCI-compatible INTx Emulation Section 6.1.3 INTx Emulation Software Model Section 6.1.4 MSI and MSI-X Operation Section 6.1.4.1 MSI Configuration Section 6.1.4.2 MSI-X Configuration Section 6.1.4.3 Enabling Operation Section 6.1.4.4 Sending Messages Section 6.1.4.5 Per-vector Masking and Function Masking Section 6.1.4.6 Hardware/Software Synchronization Section 6.1.4.7 Message Transaction Reception and Ordering Requirements Section 6.1.5 PME Support Section 6.1.6 Native PME Software Model Section 6.1.7 Legacy PME Software Model Section 6.1.8 Operating System Power Management Notification Section 6.1.9 PME Routing Between PCI Express and PCI Hierarchies Section 6.2 Error Signaling and Logging Section 6.2.1 Scope Section 6.2.2 Error Classification Section 6.2.2.1 Correctable Errors Section 6.2.2.2 Uncorrectable Errors Section 6.2.2.2.1 Fatal Errors Section 6.2.2.2.2 Non-Fatal Errors Section 6.2.3 Error Signaling Section 6.2.3.1 Completion Status Section 6.2.3.2 Error Messages Section 6.2.3.2.1 Uncorrectable Error Severity Programming (Advanced Error Reporting) Section 6.2.3.2.2 Masking Individual Errors Section 6.2.3.2.3 Error Pollution Section 6.2.3.2.4 Advisory Non-Fatal Error Cases Section 6.2.3.2.4.1 Completer Sending a Completion with UR/CA Status Section 6.2.3.2.4.2 Intermediate Receiver Section 6.2.3.2.4.3 Ultimate PCI Express Receiver of a Poisoned TLP or IDE TLP with PCRC Check Failed Section 6.2.3.2.4.4 Requester with Completion Timeout Section 6.2.3.2.4.5 Receiver of an Unexpected Completion Section 6.2.3.2.5 Requester Receiving a Completion with UR/CA Status Section 6.2.3.3 Error Forwarding (Data Poisoning) Section 6.2.3.4 Optional Error Checking Section 6.2.4 Error Logging Section 6.2.4.1 Root Complex Considerations (Advanced Error Reporting) Section 6.2.4.1.1 Error Source Identification Section 6.2.4.1.2 Interrupt Generation Section 6.2.4.2 Multiple Error Handling (Advanced Error Reporting Capability) Section 6.2.4.2.1 Multiple Error Handling in VFs Section 6.2.4.3 Advisory Non-Fatal Error Logging Section 6.2.4.4 End-End TLP Prefix Logging - Non-Flit Mode Section 6.2.5 Sequence of Device Error Signaling and Logging Operations Section 6.2.6 Error Message Controls Section 6.2.7 Error Listing and Rules Section 6.2.7.1 Conventional PCI Mapping Section 6.2.8 Virtual PCI Bridge Error Handling Section 6.2.8.1 Error Message Forwarding and PCI Mapping for Bridge - Rules Section 6.2.9 SR-IOV Baseline Error Handling Section 6.2.10 Internal Errors Section 6.2.11 Downstream Port Containment (DPC) Section 6.2.11.1 DPC Interrupts Section 6.2.11.2 DPC ERR_COR Signaling Section 6.2.11.3 Root Port Programmed I/O (RP PIO) Error Controls Section 6.2.11.4 Software Triggering of DPC Section 6.2.11.5 DL_Active ERR_COR Signaling Section 6.3 Virtual Channel Support Section 6.3.1 Introduction and Scope Section 6.3.2 TC/VC Mapping and Example Usage Section 6.3.3 VC Arbitration Section 6.3.3.1 Traffic Flow and Switch Arbitration Model Section 6.3.3.2 VC Arbitration - Arbitration Between VCs Section 6.3.3.2.1 Strict Priority Arbitration Model Section 6.3.3.2.2 Round Robin Arbitration Model Section 6.3.3.3 Port Arbitration - Arbitration Within VC Section 6.3.3.4 Multi-Function Devices and Function Arbitration Section 6.3.4 Isochronous Support Section 6.3.4.1 Rules for Software Configuration Section 6.3.4.2 Rules for Requesters Section 6.3.4.3 Rules for Completers Section 6.3.4.4 Rules for Switches and Root Complexes Section 6.3.4.5 Rules for Multi-Function Devices Section 6.4 Device Synchronization Section 6.5 Locked Transactions Section 6.5.1 Introduction Section 6.5.2 Initiation and Propagation of Locked Transactions - Rules Section 6.5.3 Switches and Lock - Rules Section 6.5.4 PCI Express/PCI Bridges and Lock - Rules Section 6.5.5 Root Complex and Lock - Rules Section 6.5.6 Legacy Endpoints Section 6.5.7 PCI Express Endpoints Section 6.6 PCI Express Reset - Rules Section 6.6.1 Conventional Reset Section 6.6.2 Function Level Reset (FLR) Section 6.7 PCI Express Native Hot-Plug Section 6.7.1 Elements of Hot-Plug Section 6.7.1.1 Indicators Section 6.7.1.1.1 Attention Indicator Section 6.7.1.1.2 Power Indicator Section 6.7.1.2 Manually-operated Retention Latch (MRL) Section 6.7.1.3 MRL Sensor Section 6.7.1.4 Electromechanical Interlock Section 6.7.1.5 Attention Button Section 6.7.1.6 Software User Interface Section 6.7.1.7 Slot Numbering Section 6.7.1.8 Power Controller Section 6.7.2 Registers Grouped by Hot-Plug Element Association Section 6.7.2.1 Attention Button Registers Section 6.7.2.2 Attention Indicator Registers Section 6.7.2.3 Power Indicator Registers Section 6.7.2.4 Power Controller Registers Section 6.7.2.5 Presence Detect Registers Section 6.7.2.6 MRL Sensor Registers Section 6.7.2.7 Electromechanical Interlock Registers Section 6.7.2.8 Command Completed Registers Section 6.7.2.9 Port Capabilities and Slot Information Registers Section 6.7.2.10 Hot-Plug Interrupt Control Register Section 6.7.3 PCI Express Hot-Plug Events Section 6.7.3.1 Slot Events Section 6.7.3.2 Command Completed Events Section 6.7.3.3 Data Link Layer State Changed Events Section 6.7.3.4 Software Notification of Hot-Plug Events Section 6.7.4 System Firmware Intermediary (SFI) Support Section 6.7.4.1 SFI ERR_COR Event Signaling Section 6.7.4.2 SFI Downstream Port Filtering (DPF) Section 6.7.4.3 SFI CAM Section 6.7.4.4 SFI Interactions with Readiness Notifications Section 6.7.4.5 SFI Suppression of Hot-Plug Surprise Functionality Section 6.7.5 Firmware Support for Hot-Plug Section 6.7.6 Async Removal Section 6.8 Power Budgeting Mechanism Section 6.8.1 System Power Budgeting Process Recommendations Section 6.8.2 Device Power Considerations Section 6.8.3 Power Limit Mechanismsm Section 6.9 Slot Power Limit Control Section 6.10 Root Complex Topology Discovery Section 6.11 Link Speed Management Section 6.12 Access Control Services (ACS) Section 6.12.1 ACS Component Capability Requirements Section 6.12.1.1 ACS Downstream Ports Section 6.12.1.2 ACS Functions in SR-IOV Capable and Multi-Function Devices Section 6.12.1.3 Functions in Single-Function Devices Section 6.12.2 Interoperability Section 6.12.3 ACS Peer-to-Peer Control Interactions Section 6.12.4 ACS Enhanced Capability Section 6.12.5 ACS Violation Error Handling Section 6.12.6 ACS Redirection Impacts on Ordering Rules Section 6.12.6.1 Completions Passing Posted Requests Section 6.12.6.2 Requests Passing Posted Requests Section 6.13 Alternative Routing-ID Interpretation (ARI) Section 6.14 Multicast Operations Section 6.14.1 Multicast TLP Processing Section 6.14.2 Multicast Ordering Section 6.14.3 Multicast Capability Structure Field Updates Section 6.14.4 MC Blocked TLP Processing Section 6.14.5 MC_Overlay Mechanism Section 6.15 Atomic Operations (AtomicOps) Section 6.15.1 AtomicOp Use Models and Benefits Section 6.15.2 AtomicOp Transaction Protocol Summary Section 6.15.3 Root Complex Support for AtomicOps Section 6.15.3.1 Root Ports with AtomicOp Completer Capabilities Section 6.15.3.2 Root Ports with AtomicOp Routing Capability Section 6.15.3.3 RCs with AtomicOp Requester Capabilities Section 6.15.4 Switch Support for AtomicOps Section 6.16 Dynamic Power Allocation (DPA) Capability Section 6.16.1 DPA Capability with Multi-Function Devices Section 6.17 TLP Processing Hints (TPH) Section 6.17.1 Processing Hints Section 6.17.2 Steering Tags Section 6.17.3 ST Modes of Operation Section 6.17.4 TPH Capability Section 6.18 Latency Tolerance Reporting (LTR) Mechanism Section 6.19 Optimized Buffer Flush/Fill (OBFF) Mechanism Section 6.20 PASID Section 6.20.1 Managing PASID Usage Section 6.20.2 PASID Information Layout Section 6.20.2.1 PASID TLP Prefix - Non-Flit Mode Section 6.20.2.2 PASID field (Flit Mode and Non-Flit Mode) Section 6.20.2.3 Execute Requested Section 6.20.2.4 Privileged Mode Requested Section 6.21 Precision Time Measurement (PTM) Mechanism Section 6.21.1 Introduction Section 6.21.2 PTM Link Protocol Section 6.21.3 Configuration and Operational Requirements Section 6.21.3.1 PTM Requester Role Section 6.21.3.2 PTM Responder Role Section 6.21.3.3 PTM Time Source Role - Rules Specific to Switches Section 6.22 Readiness Notifications (RN) Section 6.22.1 Device Readiness Status (DRS) Section 6.22.2 Function Readiness Status (FRS) Section 6.22.3 FRS Queuing Section 6.23 Enhanced Allocation Section 6.24 Emergency Power Reduction State Section 6.25 Hierarchy ID Message Section 6.26 Flattening Portal Bridge (FPB) Section 6.26.1 Introduction Section 6.26.2 Hardware and Software Requirements Section 6.27 Vital Product Data (VPD) Section 6.27.1 VPD Format Section 6.27.2 VPD Definitions Section 6.27.2.1 VPD Large and Small Resource Data Tags Section 6.27.2.2 Read-Only Fields Section 6.27.2.3 Read/Write Fields Section 6.27.2.4 VPD Example Section 6.28 Native PCIe Enclosure Management Section 6.29 Conventional PCI Advanced Features Operation Section 6.30 Data Object Exchange (DOE) Section 6.30.1 Data Objects Section 6.30.1.1 DOE Discovery Data Object Protocol Section 6.30.2 Operation Section 6.30.3 Interrupt Generation Section 6.31 Component Measurement and Authentication (CMA/SPDM) Section 6.31.1 Authenticating Component Firmware Identity Through Measurement Section 6.31.2 Authenticating Component Hardware Identity Section 6.31.3 CMA/SPDM Rules Section 6.31.4 Secured CMA/SPDM Section 6.32 Deferrable Memory Write Section 6.33 Integrity & Data Encryption (IDE) Section 6.33.1 IDE Stream and TEE State Machines Section 6.33.2 IDE Stream Establishment Section 6.33.3 IDE Key Management (IDE_KM) Section 6.33.4 IDE TLPs Section 6.33.5 IDE TLP Sub-Streams Section 6.33.6 IDE TLP Aggregation Section 6.33.7 Flow-Through Selecive IDE Streams Section 6.33.8 Other IDE Rules Chapter 7. Software Initialization and Configuration Section 7.1 Configuration Topology Section 7.2 PCI Express Configuration Mechanisms Section 7.2.1 PCI-compatible Configuration Mechanism Section 7.2.2 PCI Express Enhanced Configuration Access Mechanism (ECAM) Section 7.2.2.1 Host Bridge Requirements Section 7.2.2.2 PCI Express Device Requirements Section 7.2.3 Root Complex Register Block (RCRB) Section 7.3 Configuration Transaction Rules Section 7.3.1 Device Number Section 7.3.2 Configuration Transaction Addressing Section 7.3.3 Configuration Request Routing Rules Section 7.3.4 PCI Special Cycles Section 7.4 Configuration Register Types Section 7.5 PCI and PCIe Capabilities Required by the Base Spec for all Ports Section 7.5.1 PCI-Compatible Configuration Registers Section 7.5.1.1 Type 0/1 Common Configuration Space Section 7.5.1.1.1 Vendor ID Register (Offset 00h) Section 7.5.1.1.2 Device ID Register (Offset 02h) Section 7.5.1.1.3 Command Register (Offset 04h) Section 7.5.1.1.4 Status Register (Offset 06h) Section 7.5.1.1.5 Revision ID Register (Offset 08h) Section 7.5.1.1.6 Class Code Register (Offset 09h) Section 7.5.1.1.7 Cache Line Size Register (Offset 0Ch) Section 7.5.1.1.8 Latency Timer Register (Offset 0Dh) Section 7.5.1.1.9 Header Type Register (Offset 0Eh) Section 7.5.1.1.10 BIST Register (Offset 0Fh) Section 7.5.1.1.11 Capabilities Pointer (Offset 34h) Section 7.5.1.1.12 Interrupt Line Register (Offset 3Ch) Section 7.5.1.1.13 Interrupt Pin Register (Offset 3Dh) Section 7.5.1.1.14 Error Registers Section 7.5.1.2 Type 0 Configuration Space Header Section 7.5.1.2.1 Base Address Registers (Offset 10h - 24h) Section 7.5.1.2.2 Cardbus CIS Pointer Register (Offset 28h) Section 7.5.1.2.3 Subsystem Vendor ID Register/Subsystem ID Register (Offset 2Ch/2Eh) Section 7.5.1.2.4 Expansion ROM Base Address Register (Offset 30h) Section 7.5.1.2.5 Min_Gnt Register/Max_Lat Register (Offset 3Eh/3Fh) Section 7.5.1.3 Type 1 Configuration Space Header Section 7.5.1.3.1 Type 1 Base Address Registers (Offset 10h-14h) Section 7.5.1.3.2 Primary Bus Number Register (Offset 18h) Section 7.5.1.3.3 Secondary Bus Number Register (Offset 19h) Section 7.5.1.3.4 Subordinate Bus Number Register (Offset 1Ah) Section 7.5.1.3.5 Secondary Latency Timer (Offset 1Bh) Section 7.5.1.3.6 I/O Base/I/O Limit Registers(Offset 1Ch/1Dh) Section 7.5.1.3.7 Secondary Status Register (Offset 1Eh) Section 7.5.1.3.8 Memory Base Register/Memory Limit Register(Offset 20h/22h) Section 7.5.1.3.9 Prefetchable Memory Base/Prefetchable Memory Limit Registers (Offset 24h/26h) Section 7.5.1.3.10 Prefetchable Base Upper 32 Bits/Prefetchable Limit Upper 32 Bits Registers (Offset 28h/2Ch) Section 7.5.1.3.11 I/O Base Upper 16 Bits/I/O Limit Upper 16 Bits Registers (Offset 30h/32h) Section 7.5.1.3.12 Expansion ROM Base Address Register (Offset 38h) Section 7.5.1.3.13 Bridge Control Register (Offset 3Eh) Section 7.5.2 PCI Power Management Capability Structure Section 7.5.2.1 Power Management Capabilities Register (Offset 00h) Section 7.5.2.2 Power Management Control/Status Register (Offset 04h) Section 7.5.2.3 Power Management Data Register (Offset 07h) Section 7.5.3 PCI Express Capability Structure Section 7.5.3.1 PCI Express Capability List Register (Offset 00h) Section 7.5.3.2 PCI Express Capabilities Register (Offset 02h) Section 7.5.3.3 Device Capabilities Register (Offset 04h) Section 7.5.3.4 Device Control Register (Offset 08h) Section 7.5.3.5 Device Status Register (Offset 0Ah) Section 7.5.3.6 Link Capabilities Register (Offset 0Ch) Section 7.5.3.7 Link Control Register (Offset 10h) Section 7.5.3.8 Link Status Register (Offset 12h) Section 7.5.3.9 Slot Capabilities Register (Offset 14h) Section 7.5.3.10 Slot Control Register (Offset 18h) Section 7.5.3.11 Slot Status Register (Offset 1Ah) Section 7.5.3.12 Root Control Register (Offset 1Ch) Section 7.5.3.13 Root Capabilities Register (Offset 1Eh) Section 7.5.3.14 Root Status Register (Offset 20h) Section 7.5.3.15 Device Capabilities 2 Register (Offset 24h) Section 7.5.3.16 Device Control 2 Register (Offset 28h) Section 7.5.3.17 Device Status 2 Register (Offset 2Ah) Section 7.5.3.18 Link Capabilities 2 Register (Offset 2Ch) Section 7.5.3.19 Link Control 2 Register (Offset 30h) Section 7.5.3.20 Link Status 2 Register (Offset 32h) Section 7.5.3.21 Slot Capabilities 2 Register (Offset 34h) Section 7.5.3.22 Slot Control 2 Register (Offset 38h) Section 7.5.3.23 Slot Status 2 Register (Offset 3Ah) Section 7.6 PCI Express Extended Capabilities Section 7.6.1 Extended Capabilities in Configuration Space Section 7.6.2 Extended Capabilities in the Root Complex Register Block Section 7.6.3 PCI Express Extended Capability Header Section 7.7 PCI and PCIe Capabilities Required by the Base Spec in Some Situations Section 7.7.1 MSI Capability Structures Section 7.7.1.1 MSI Capability Header (Offset 00h) Section 7.7.1.2 Message Control Register for MSI (Offset 02h) Section 7.7.1.3 Message Address Register for MSI (Offset 04h) Section 7.7.1.4 Message Upper Address Register for MSI (Offset 08h) Section 7.7.1.5 Message Data Register for MSI (Offset 08h or 0Ch) Section 7.7.1.6 Extended Message Data Register for MSI (Optional) Section 7.7.1.7 Mask Bits Register for MSI (Offset 0Ch or 10h Section 7.7.1.8 Pending Bits Register for MSI (Offset 10h or 14h) Section 7.7.2 MSI-X Capability and Table Structure Section 7.7.2.1 MSI-X Capability Header (Offset 00h) Section 7.7.2.2 Message Control Register for MSI-X (Offset 02h) Section 7.7.2.3 Table Offset/Table BIR Register for MSI-X (Offset 04h) Section 7.7.2.4 PBA Offset/PBA BIR Register for MSI-X (Offset 08h) Section 7.7.2.5 Message Address Register for MSI-X Table Entries Section 7.7.2.6 Message Upper Address Register for MSI-X Table Entries Section 7.7.2.7 Message Data Register for MSI-X Table Entries Section 7.7.2.8 Vector Control Register for MSI-X Table Entries Section 7.7.2.9 Pending Bits Register for MSI-X PBA Entries Section 7.7.3 Secondary PCI Express Extended Capability Section 7.7.3.1 Secondary PCI Express Extended Capability Header (Offset 00h) Section 7.7.3.2 Link Control 3 Register (Offset 04h) Section 7.7.3.3 Lane Error Status Register (Offset 08h) Section 7.7.3.4 Lane Equalization Control Register (Offset 0Ch) Section 7.7.4 Data Link Feature Extended Capability Section 7.7.4.1 Data Link Feature Extended Capability Header (Offset 00h) Section 7.7.4.2 Data Link Feature Capabilities Register (Offset 04h) Section 7.7.4.3 Data Link Feature Status Register (Offset 08h) Section 7.7.5 Physical Layer 16.0 GT/s Extended Capability Section 7.7.5.1 Physical Layer 16.0 GT/s Extended Capability Header (Offset 00h) Section 7.7.5.2     16.0 GT/s Capabilities Register (Offset 04h) Section 7.7.5.3     16.0 GT/s Control Register (Offset 08h) Section 7.7.5.4     16.0 GT/s Status Register (Offset 0Ch) Section 7.7.5.5     16.0 GT/s Local Data Parity Mismatch Status Register (Offset 10h) Section 7.7.5.6     16.0 GT/s First Retimer Data Parity Mismatch Status Register (Offset 14h) Section 7.7.5.7     16.0 GT/s Second Retimer Data Parity Mismatch Status Register (Offset 18h) Section 7.7.5.8 Physical Layer 16.0 GT/s Reserved (Offset 1Ch) Section 7.7.5.9     16.0 GT/s Lane Equalization Control Register (Offsets 20h to 3Ch) Section 7.7.6 Physical Layer 32.0 GT/s Extended Capability Section 7.7.6.1 Physical Layer 32.0 GT/s Extended Capability Header (Offset 00h) Section 7.7.6.2     32.0 GT/s Capabilities Register (Offset 04h) Section 7.7.6.3     32.0 GT/s Control Register (Offset 08h) Section 7.7.6.4     32.0 GT/s Status Register (Offset 0Ch) Section 7.7.6.5 Received Modified TS Data 1 Register (Offset 10h) Section 7.7.6.6 Received Modified TS Data 2 Register (Offset 14h) Section 7.7.6.7 Transmitted Modified TS Data 1 Register (Offset 18h) Section 7.7.6.8 Transmitted Modified TS Data 2 Register (Offset 1Ch) Section 7.7.6.9     32.0 GT/s Lane Equalization Control Register (Offset 20h) Section 7.7.7 Physical Layer 64.0 GT/s Extended Capability Section 7.7.7.1 Physical Layer 64.0 GT/s Extended Capability Header (Offset 00h) Section 7.7.7.2     64.0 GT/s Capabilities Register (Offset 04h) Section 7.7.7.3     64.0 GT/s Control Register (Offset 08h) Section 7.7.7.4     64.0 GT/s Status Register (Offset 0Ch) Section 7.7.7.5     64.0 GT/s Lane Equalization Control Register (Offset 20h) Section 7.7.8 Flit Logging Extended Capability Section 7.7.8.1 Flit Logging Extended Capability Header (Offset 00h) Section 7.7.8.2 Flit Error Log 1 Register (Offset 04h) Section 7.7.8.3 Flit Error Log 2 Register (Offset 08h) Section 7.7.8.4 Flit Error Counter Control Register (Offset 0Ch) Section 7.7.8.5 Flit Error Counter Status Register (Offset 0Eh) Section 7.7.8.6 FBER Measurement Control Register (Offset 10h) Section 7.7.8.7 FBER Measurement Status 1 Register (Offset 14h) Section 7.7.8.8 FBER Measurement Status 2 Register (Offset 18h) Section 7.7.8.9 FBER Measurement Status 3 Register (Offset 1Ch) Section 7.7.8.10 FBER Measurement Status 4 Register (Offset 20h) Section 7.7.8.11 FBER Measurement Status 5 Register (Offset 24h) Section 7.7.8.12 FBER Measurement Status 6 Register (Offset 28h) Section 7.7.8.13 FBER Measurement Status 7 Register (Offset 2Ch) Section 7.7.8.14 FBER Measurement Status 8 Register (Offset 30h) Section 7.7.8.15 FBER Measurement Status 9 Register (Offset 34h) Section 7.7.8.16 FBER Measurement Status 10 Register (Offset 38h) Section 7.7.9 Device 3 Extended Capability Structure Section 7.7.9.1 Device 3 Extended Capability Header (Offset 00h) Section 7.7.9.2 Device Capabilities 3 Register (Offset 04h) Section 7.7.9.3 Device Control 3 Register (Offset 08h) Section 7.7.9.4 Device Status 3 Register (Offset 0Ch) Section 7.7.10 Lane Margining at the Receiver Extended Capability Section 7.7.10.1 Lane Margining at the Receiver Extended Capability Header (Offset 00h) Section 7.7.10.2 Margining Port Capabilities Register (Offset 04h) Section 7.7.10.3 Margining Port Status Register (Offset 06h) Section 7.7.10.4 Margining Lane Control Register (Offset 08h) Section 7.7.10.5 Margining Lane Status Register (Offset 0Ah) Section 7.7.11 ACS Extended Capability Section 7.7.11.1 ACS Extended Capability Header (Offset 00h) Section 7.7.11.2 ACS Capability Register (Offset 04h) Section 7.7.11.3 ACS Control Register (Offset 06h) Section 7.7.11.4 Egress Control Vector Register (Offset 08h) Section 7.8 Common PCI and PCIe Capabilities Section 7.8.1 Power Budgeting Extended Capability Section 7.8.1.1 Power Budgeting Extended Capability Header (Offset 00h) Section 7.8.1.2 Power Budgeting Data Select Register (Offset 04h) Section 7.8.1.3 Power Budgeting Control Register (Offset 06h) Section 7.8.1.4 Power Budgeting Data Register (Offset 08h) Section 7.8.1.5 Power Budgeting Capability Register (Offset 0Ch) Section 7.8.1.6 Power Budgeting Sense Detect Register (Offset 0Dh) Section 7.8.2 Latency Tolerance Reporting (LTR) Extended Capability Section 7.8.2.1 LTR Extended Capability Header (Offset 00h) Section 7.8.2.2 Max Snoop Latency Register (Offset 04h) Section 7.8.2.3 Max No-Snoop Latency Register (Offset 06h) Section 7.8.3 L1 PM Substates Extended Capability Section 7.8.3.1 L1 PM Substates Extended Capability Header (Offset 00h) Section 7.8.3.2 L1 PM Substates Capabilities Register (Offset 04h) Section 7.8.3.3 L1 PM Substates Control 1 Register (Offset 08h) Section 7.8.3.4 L1 PM Substates Control 2 Register (Offset 0Ch) Section 7.8.3.5 L1 PM Substates Status Register (Offset 10h) Section 7.8.4 Advanced Error Reporting Extended Capability Section 7.8.4.1 Advanced Error Reporting Extended Capability Header (Offset 00h) Section 7.8.4.2 Uncorrectable Error Status Register (Offset 04h) Section 7.8.4.3 Uncorrectable Error Mask Register (Offset 08h) Section 7.8.4.4 Uncorrectable Error Severity Register (Offset 0Ch) Section 7.8.4.5 Correctable Error Status Register (Offset 10h) Section 7.8.4.6 Correctable Error Mask Register (Offset 14h) Section 7.8.4.7 Advanced Error Capabilities and Control Register (Offset 18h) Section 7.8.4.8 Header Log Register (Offset 1Ch) Section 7.8.4.9 Root Error Command Register (Offset 2Ch) Section 7.8.4.10 Root Error Status Register (Offset 30h) Section 7.8.4.11 Error Source Identification Register (Offset 34h) Section 7.8.4.12 TLP Prefix Log Register (Offset 38h) Section 7.8.5 Enhanced Allocation Capability Structure (EA) Section 7.8.5.1 Enhanced Allocation Capability First DW (Offset 00h) Section 7.8.5.2 Enhanced Allocation Capability Second DW (Offset 04h) [Type 1 Functions Only] Section 7.8.5.3 Enhanced Allocation Per-Entry Format (Offset 04h or 08h) Section 7.8.6 Resizable BAR Extended Capability Section 7.8.6.1 Resizable BAR Extended Capability Header (Offset 00h) Section 7.8.6.2 Resizable BAR Capability Register Section 7.8.6.3 Resizable BAR Control Register Section 7.8.7 VF Resizable BAR Extended Capability Section 7.8.7.1 VF Resizable BAR Extended Capability Header (Offset 00h) Section 7.8.7.2 VF Resizable BAR Capability Register (Offset 04h) Section 7.8.7.3 VF Resizable BAR Control Register (Offset 08h) Section 7.8.8 ARI Extended Capability Section 7.8.8.1 ARI Extended Capability Header (Offset 00h) Section 7.8.8.2 ARI Capability Register (Offset 04h) Section 7.8.8.3 ARI Control Register (Offset 06h) Section 7.8.9 PASID Extended Capability Structure Section 7.8.9.1 PASID Extended Capability Header (Offset 00h) Section 7.8.9.2 PASID Capability Register (Offset 04h) Section 7.8.9.3 PASID Control Register (Offset 06h) Section 7.8.10 FRS Queueing Extended Capability Section 7.8.10.1 FRS Queueing Extended Capability Header (Offset 00h) Section 7.8.10.2 FRS Queueing Capability Register (Offset 04h) Section 7.8.10.3 FRS Queueing Status Register (Offset 08h) Section 7.8.10.4 FRS Queueing Control Register (Offset 0Ah) Section 7.8.10.5 FRS Message Queue Register (Offset 0Ch) Section 7.8.11 Flattening Portal Bridge (FPB) Capability Section 7.8.11.1 FPB Capability Header (Offset 00h) Section 7.8.11.2 FPB Capabilities Register (Offset 04h) Section 7.8.11.3 FPB RID Vector Control 1 Register (Offset 08h) Section 7.8.11.4 FPB RID Vector Control 2 Register (Offset 0Ch) Section 7.8.11.5 FPB MEM Low Vector Control Register (Offset 10h) Section 7.8.11.6 FPB MEM High Vector Control 1 Register (Offset 14h) Section 7.8.11.7 FPB MEM High Vector Control 2 Register (Offset 18h) Section 7.8.11.8 FPB Vector Access Control Register (Offset 1Ch) Section 7.8.11.9 FPB Vector Access Data Register (Offset 20h) Section 7.8.12 Flit Performance Measurement Extended Capability Section 7.8.12.1 Flit Performance Measurement Extended Capability Header (Offset 00h) Section 7.8.12.2 Flit Performance Measurement Capability Register (Offset 04h) Section 7.8.12.3 Flit Performance Measurement Control Register (Offset 08h) Section 7.8.12.4 Flit Performance Measurement Status Register (Offset 0Ch) Section 7.8.12.5 LTSSM Performance Measurement Status Register (Offsets 10h to 20h) Section 7.8.13 Flit Error Injection Extended Capability Section 7.8.13.1 Flit Error Injection Extended Capability Header (Offset 00h) Section 7.8.13.2 Flit Error Injection Capability Register (Offset 04h) Section 7.8.13.3 Flit Error Injection Control 1 Register (Offset 08h) Section 7.8.13.4 Flit Error Injection Control 2 Register (Offset 0Ch) Section 7.8.13.5 Flit Error Injection Status Register (Offset 10h) Section 7.8.13.6 Ordered Set Error Injection Control 1 Register (Offset 14h) Section 7.8.13.7 Ordered Set Error Injection Control 2 Register (Offset 18h) Section 7.8.13.8 Ordered Set Error Tx Injection Status Register (Offset 1Ch) Section 7.8.13.9 Ordered Set Error Rx Injection Status Register (Offset 20h) Section 7.9 Additional PCI and PCIe Capabilities Section 7.9.1 Virtual Channel Extended Capability Section 7.9.1.1 Virtual Channel Extended Capability Header (Offset 00h) Section 7.9.1.2 Port VC Capability Register 1 (Offset 04h) Section 7.9.1.3 Port VC Capability Register 2 (Offset 08h) Section 7.9.1.4 Port VC Control Register (Offset 0Ch) Section 7.9.1.5 Port VC Status Register (Offset 0Eh) Section 7.9.1.6 VC Resource Capability Register Section 7.9.1.7 VC Resource Control Register Section 7.9.1.8 VC Resource Status Register Section 7.9.1.9 VC Arbitration Table Section 7.9.1.10 Port Arbitration Table Section 7.9.2 Multi-Function Virtual Channel Extended Capability Section 7.9.2.1 MFVC Extended Capability Header (Offset 00h) Section 7.9.2.2 MFVC Port VC Capability Register 1 (Offset 04h) Section 7.9.2.3 MFVC Port VC Capability Register 2 (Offset 08h) Section 7.9.2.4 MFVC Port VC Control Register (Offset 0Ch) Section 7.9.2.5 MFVC Port VC Status Register (Offset 0Eh) Section 7.9.2.6 MFVC VC Resource Capability Register Section 7.9.2.7 MFVC VC Resource Control Register Section 7.9.2.8 MFVC VC Resource Status Register Section 7.9.2.9 MFVC VC Arbitration Table Section 7.9.2.10 Function Arbitration Table Section 7.9.3 Device Serial Number Extended Capability Section 7.9.3.1 Device Serial Number Extended Capability Header (Offset 00h) Section 7.9.3.2 Serial Number Register (Offset 04h) Section 7.9.4 Vendor-Specific Capability Section 7.9.5 Vendor-Specific Extended Capability Section 7.9.5.1 Vendor-Specific Extended Capability Header (Offset 00h) Section 7.9.5.2 Vendor-Specific Header (Offset 04h) Section 7.9.6 Designated Vendor-Specific Extended Capability (DVSEC) Section 7.9.6.1 Designated Vendor-Specific Extended Capability Header (Offset 00h) Section 7.9.6.2 Designated Vendor-Specific Header 1 (Offset 04h) Section 7.9.6.3 Designated Vendor-Specific Header 2 (Offset 08h) Section 7.9.7 RCRB Header Extended Capability Section 7.9.7.1 RCRB Header Extended Capability Header (Offset 00h) Section 7.9.7.2 RCRB Vendor ID and Device ID register (Offset 04h) Section 7.9.7.3 RCRB Capabilities register (Offset 08h) Section 7.9.7.4 RCRB Control register (Offset 0Ch) Section 7.9.8 Root Complex Link Declaration Extended Capability Section 7.9.8.1 Root Complex Link Declaration Extended Capability Header (Offset 00h) Section 7.9.8.2 Element Self Description Register (Offset 04h) Section 7.9.8.3 Link Entries Section 7.9.8.3.1 Link Description Register Section 7.9.8.3.2 Link Address Section 7.9.8.3.2.1 Link Address for Link Type 0 Section 7.9.8.3.2.2 Link Address for Link Type 1 Section 7.9.9 Root Complex Internal Link Control Extended Capability Section 7.9.9.1 Root Complex Internal Link Control Extended Capability Header (Offset 00h) Section 7.9.9.2 Root Complex Link Capabilities Register (Offset 04h) Section 7.9.9.3 Root Complex Link Control Register (Offset 08h) Section 7.9.9.4 Root Complex Link Status Register (Offset 0Ah) Section 7.9.10 Root Complex Event Collector Endpoint Association Extended Capability Section 7.9.10.1 Root Complex Event Collector Endpoint Association Extended Capability Header (Offset 00h) Section 7.9.10.2 Association Bitmap for RCiEPs (Offset 04h) Section 7.9.10.3 RCEC Associated Bus Numbers Register (Offset 08h) Section 7.9.11 Multicast Extended Capability Section 7.9.11.1 Multicast Extended Capability Header (Offset 00h) Section 7.9.11.2 Multicast Capability Register (Offset 04h) Section 7.9.11.3 Multicast Control Register (Offset 06h) Section 7.9.11.4 MC_Base_Address Register (Offset 08h) Section 7.9.11.5 MC_Receive Register (Offset 10h) Section 7.9.11.6 MC_Block_All Register (Offset 18h) Section 7.9.11.7 MC_Block_Untranslated Register (Offset 20h) Section 7.9.11.8 MC_Overlay_BAR Register (Offset 28h) Section 7.9.12 Dynamic Power Allocation Extended Capability (DPA Capability) Section 7.9.12.1 DPA Extended Capability Header (Offset 00h) Section 7.9.12.2 DPA Capability Register (Offset 04h) Section 7.9.12.3 DPA Latency Indicator Register (Offset 08h) Section 7.9.12.4 DPA Status Register (Offset 0Ch) Section 7.9.12.5 DPA Control Register (Offset 0Eh) Section 7.9.12.6 DPA Power Allocation Array Section 7.9.13 TPH Requester Extended Capability Section 7.9.13.1 TPH Requester Extended Capability Header (Offset 00h) Section 7.9.13.2 TPH Requester Capability Register (Offset 04h) Section 7.9.13.3 TPH Requester Control Register (Offset 08h) Section 7.9.13.4 TPH ST Table (Starting from Offset 0Ch) Section 7.9.14 DPC Extended Capability Section 7.9.14.1 DPC Extended Capability Header (Offset 00h) Section 7.9.14.2 DPC Capability Register (Offset 04h) Section 7.9.14.3 DPC Control Register (Offset 06h) Section 7.9.14.4 DPC Status Register (Offset 08h) Section 7.9.14.5 DPC Error Source ID Register (Offset 0Ah) Section 7.9.14.6 RP PIO Status Register (Offset 0Ch) Section 7.9.14.7 RP PIO Mask Register (Offset 10h) Section 7.9.14.8 RP PIO Severity Register (Offset 14h) Section 7.9.14.9 RP PIO SysError Register (Offset 18h) Section 7.9.14.10 RP PIO Exception Register (Offset 1Ch) Section 7.9.14.11 RP PIO Header Log Register (Offset 20h) Section 7.9.14.12 RP PIO ImpSpec Log Register (Offset 30h) Section 7.9.14.13 RP PIO TLP Prefix Log Register (Offset 34h) Section 7.9.15 Precision Time Management Extended Capability (PTM Capability) Section 7.9.15.1 PTM Extended Capability Header (Offset 00h) Section 7.9.15.2 PTM Capability Register (Offset 04h) Section 7.9.15.3 PTM Control Register (Offset 08h) Section 7.9.16 Readiness Time Reporting Extended Capability Section 7.9.16.1 Readiness Time Reporting Extended Capability Header (Offset 00h) Section 7.9.16.2 Readiness Time Reporting 1 Register (Offset 04h) Section 7.9.16.3 Readiness Time Reporting 2 Register (Offset 08h) Section 7.9.17 Hierarchy ID Extended Capability Section 7.9.17.1 Hierarchy ID Extended Capability Header (Offset 00h) Section 7.9.17.2 Hierarchy ID Status Register (Offset 04h) Section 7.9.17.3 Hierarchy ID Data Register (Offset 08h) Section 7.9.17.4 Hierarchy ID GUID 1 Register (Offset 0Ch) Section 7.9.17.5 Hierarchy ID GUID 2 Register (Offset 10h) Section 7.9.17.6 Hierarchy ID GUID 3 Register (Offset 14h) Section 7.9.17.7 Hierarchy ID GUID 4 Register (Offset 18h) Section 7.9.17.8 Hierarchy ID GUID 5 Register (Offset 1Ch) Section 7.9.18 Vital Product Data Capability (VPD Capability) Section 7.9.18.1 VPD Address Register Section 7.9.18.2 VPD Data Register Section 7.9.19 Native PCIe Enclosure Management Extended Capability (NPEM Extended Capability) Section 7.9.19.1 NPEM Extended Capability Header (Offset 00h) Section 7.9.19.2 NPEM Capability Register (Offset 04h) Section 7.9.19.3 NPEM Control Register (Offset 08h) Section 7.9.19.4 NPEM Status Register (Offset 0Ch) Section 7.9.20 Alternate Protocol Extended Capability Section 7.9.20.1 Alternate Protocol Extended Capability Header (Offset 00h) Section 7.9.20.2 Alternate Protocol Capabilities Register (Offset 04h) Section 7.9.20.3 Alternate Protocol Control Register (Offset 08h) Section 7.9.20.4 Alternate Protocol Data 1 Register (Offset 0Ch) Section 7.9.20.5 Alternate Protocol Data 2 Register (Offset 10h) Section 7.9.20.6 Alternate Protocol Selective Enable Mask Register (Offset 14h) Section 7.9.21 Conventional PCI Advanced Features Capability (AF) Section 7.9.21.1 Advanced Features Capability Header (Offset 00h) Section 7.9.21.2 AF Capabilities Register (Offset 03h) Section 7.9.21.3 Conventional PCI Advanced Features Control Register (Offset 04h) Section 7.9.21.4 AF Status Register (Offset 05h) Section 7.9.22 SFI Extended Capability Section 7.9.22.1 SFI Extended Capability Header (Offset 00h) Section 7.9.22.2 SFI Capability Register (Offset 04h) Section 7.9.22.3 SFI Control Register (Offset 06h) Section 7.9.22.4 SFI Status Register (Offset 08h) Section 7.9.22.5 SFI CAM Address Register (Offset 0Ch) Section 7.9.22.6 SFI CAM Data Register (Offset 10h) Section 7.9.23 Subsystem ID and Subsystem Vendor ID Capability Section 7.9.23.1 Subsystem ID and Subsystem Vendor ID Capability Header (Offset 00h) Section 7.9.23.2 Subsystem ID and Subsystem Vendor ID Capability Data (Offset 04h) Section 7.9.24 Data Object Exchange Extended Capability Section 7.9.24.1 Extended Capability Header (Offset 00h) Section 7.9.24.2 DOE Capabilities Register (Offset 04h) Section 7.9.24.3 DOE Control Register (Offset 08h) Section 7.9.24.4 DOE Status Register (Offset 0Ch) Section 7.9.24.5 DOE Write Data Mailbox Register (Offset 10h) Section 7.9.24.6 DOE Read Data Mailbox Register (Offset 14h) Section 7.9.25 Shadow Functions Extended Capability Section 7.9.25.1 Shadow Functions Extended Capability Header (Offset 00h) Section 7.9.25.2 Shadow Functions Capability Register (Offset 04h) Section 7.9.25.3 Shadow Functions Control Register (Offset 08h) Section 7.9.25.4 Shadow Functions Instance Register Entry Section 7.9.26 IDE Extended Capability Section 7.9.26.1 IDE Extended Capability Header (Offset 00h) Section 7.9.26.2 IDE Capability Register (Offset 04h) Section 7.9.26.3 IDE Control Register (Offset 08h) Section 7.9.26.4 Link IDE Register Block Section 7.9.26.4.1 Link IDE Stream Control Register Section 7.9.26.4.2 Link IDE Stream Status Register Section 7.9.26.5 Selective IDE Stream Register Block Section 7.9.26.5.1 Selective IDE Stream Capability Register Section 7.9.26.5.2 Selective IDE Stream Control Register Section 7.9.26.5.3 Selective IDE Stream Status Register Section 7.9.26.5.4 Selective IDE RID Association Register Block Section 7.9.26.5.4.1 IDE RID Association Register 1 Section 7.9.26.5.4.2 IDE RID Association Register 2 Section 7.9.26.5.5 Selective IDE Address Association Register Block Section 7.9.26.5.5.1 IDE Address Association Register 1 Section 7.9.26.5.5.2 IDE Address Association Register 2 Section 7.9.26.5.5.3 IDE Address Association Register 3 Section 7.9.27 Null Capability Section 7.9.28 Null Extended Capability Chapter 8. Electrical Sub-Block Section 8.1 Electrical Specification Introduction Section 8.2 Interoperability Criteria Section 8.2.1 Data Rates Section 8.2.2 Refclk Architectures Section 8.3 Transmitter Specification Section 8.3.1 Measurement Setup for Characterizing Transmitters Section 8.3.1.1 Breakout and Replica Channels Section 8.3.2 Voltage Level Definitions Section 8.3.3 Tx Voltage Parameters Section 8.3.3.1 2.5 and 5.0 GT/s Transmitter Equalization Section 8.3.3.2 8.0, 16.0, 32.0, and 64.0 GT/s Transmitter Equalization Section 8.3.3.3 Tx Equalization Presets for 8.0, 16.0, 32.0, and 64.0 GT/s Section 8.3.3.4 Measuring Tx Equalization for 2.5 GT/s and 5.0 GT/s Section 8.3.3.5 Measuring Presets at 8.0, 16.0, 32.0, and 64.0 GT/s Section 8.3.3.6 Method for Measuring VTX-DIFF-PP at 2.5 GT/s and 5.0 GT/s Section 8.3.3.7 Method for Measuring VTX-DIFF-PP at 8.0, 16.0, 32.0, and 64.0 GT/s Section 8.3.3.8 Coefficient Range and Tolerance for 8.0, 16.0, 32.0, and 64.0 GT/s Section 8.3.3.9 EIEOS and VTX-EIEOS-FS and VTX-EIEOS-RS Limits Section 8.3.3.10 Reduced Swing Signaling Section 8.3.3.11 Effective Tx Package Loss at 8.0, 16.0, 32.0, and 64.0 GT/s Section 8.3.3.12 Transmitter Signal-to Noise and Distortion Ratio (SNDRTX) for 64.0 GT/s Section 8.3.3.13 Transmitter Ratio of Level Mismatch (RLM-TX) for 64.0 GT/s Section 8.3.4 Transmitter Margining Section 8.3.5 Tx Jitter Parameters Section 8.3.5.1 Post Processing Steps to Extract Jitter Section 8.3.5.2 Applying CTLE or De-embedding Section 8.3.5.3 Independent Refclk Measurement and Post Processing Section 8.3.5.4 Embedded and Non-Embedded Refclk Measurement and Post Processing Section 8.3.5.5 Behavioral CDR Characteristics Section 8.3.5.6 Data Dependent and Uncorrelated Jitter Section 8.3.5.7 Data Dependent Jitter Section 8.3.5.8 Uncorrelated Total Jitter and Deterministic Jitter (Dual Dirac Model) (TTX-UTJ and TTX-UDJDD) Section 8.3.5.9 Random Jitter (TTX-RJ) (informative) Section 8.3.5.10 Uncorrelated Total and Deterministic PWJ (TTX-UPW-TJ and TTX-UPW-DJDD) Section 8.3.6 Data Rate Dependent Parameters Section 8.3.7 Tx and Rx Return Loss for 2.5, 5.0, 8.0, 16.0, and 32.0 GT/s Section 8.3.8 Tx and Rx Return Loss for 64.0 GT/s Section 8.3.9 Transmitter PLL Bandwidth and Peaking Section 8.3.9.1 2.5 GT/s and 5.0 GT/s Tx PLL Bandwidth and Peaking Section 8.3.9.2 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s Tx PLL Bandwidth and Peaking Section 8.3.9.3 Series Capacitors Section 8.3.10 Data Rate Independent Tx Parameters Section 8.4 Receiver Specifications Section 8.4.1 Receiver Stressed Eye Specification Section 8.4.1.1 Breakout and Replica Channels Section 8.4.1.2 Calibration Channel Insertion Loss Characteristics Section 8.4.1.3 Post Processing Procedures Section 8.4.1.4 Behavioral Rx Package Models Section 8.4.1.5 Behavioral CDR Model Section 8.4.1.6 No Behavioral Rx Equalization for 2.5 and 5.0 GT/s Section 8.4.1.7 Behavioral Rx Equalization for 8.0, 16.0, 32.0, and 64.0 GT/s Section 8.4.1.8 Behavioral CTLE (8.0 and 16.0 GT/s) Section 8.4.1.9 Behavioral CTLE (32.0 and 64.0 GT/s) Section 8.4.1.10 Behavioral DFE (8.0, 16.0, 32.0, and 64.0 GT/s Only) Section 8.4.2 Stressed Eye Test Section 8.4.2.1 Procedure for Calibrating a Stressed EH/EW Eye Section 8.4.2.1.1 Post Processing Tool Requirements Section 8.4.2.2 Procedure for Testing Rx DUT Section 8.4.2.2.1 Sj Mask Section 8.4.2.3 Receiver Refclk Modes Section 8.4.2.3.1 Common Refclk Mode Section 8.4.2.3.2 Independent Refclk Mode Section 8.4.3 Common Receiver Parameters Section 8.4.3.1 5.0 GT/s Exit From Idle Detect (EFI) Section 8.4.3.2 Receiver Return Loss Section 8.4.4 Lane Margining at the Receiver - Electrical Requirements Section 8.4.5 Low Frequency and Miscellaneous Signaling Requirements Section 8.4.5.1 ESD Standards Section 8.4.5.2 Channel AC Coupling Capacitors Section 8.4.5.3 Short Circuit Requirements Section 8.4.5.4 Transmitter and Receiver Termination Section 8.4.5.5 Electrical Idle Section 8.4.5.6 DC Common Mode Voltage Section 8.4.5.7 Receiver Detection Section 8.5 Channel Tolerancing Section 8.5.1 Channel Compliance Testing Section 8.5.1.1 Behavioral Transmitter and Receiver Package Models Section 8.5.1.2 Measuring Package Performance (16.0 GT/s only) Section 8.5.1.3 Simulation Tool Requirements Section 8.5.1.3.1 Simulation Tool Chain Inputs Section 8.5.1.3.2 Processing Steps Section 8.5.1.3.3 Simulation Tool Outputs Section 8.5.1.3.4 Open Source Simulation Tool Section 8.5.1.4 Behavioral Transmitter Parameters Section 8.5.1.4.1 Deriving Voltage and Jitter Parameters Section 8.5.1.4.2 Optimizing Tx/Rx Equalization (8.0, 16.0, 32.0, and 64.0 GT/s only) Section 8.5.1.4.3 Pass/Fail Eye Characteristics Section 8.5.1.4.4 Characterizing Channel Common Mode Noise Section 8.5.1.4.5 Verifying VCH-IDLE-DET-DIFF-pp Section 8.6 Refclk Specifications Section 8.6.1 Refclk Test Setup Section 8.6.2 REFCLK AC Specifications Section 8.6.3 Data Rate Independent Refclk Parameters Section 8.6.3.1 Low Frequency Refclk Jitter Limits Section 8.6.4 Refclk Architectures Supported Section 8.6.5 Filtering Functions Applied to Raw Data Section 8.6.5.1 PLL Filter Transfer Function Example Section 8.6.5.2 CDR Transfer Function Examples Section 8.6.6 Common Refclk Rx Architecture (CC) Section 8.6.6.1 Determining the Number of PLL BW and peaking Combinations Section 8.6.6.2 CDR and PLL BW and Peaking Limits for Common Refclk Section 8.6.7 Jitter Limits for Refclk Architectures Section 8.6.8 Form Factor Requirements for RefClock Architectures Chapter 9. Single Root I/O Virtualization and Sharing Section 9.1 SR-IOV Architectural Overview Section 9.2 SR-IOV Initialization and Resource Allocation Section 9.2.1 SR-IOV Resource Discovery Section 9.2.1.1 Configuring SR-IOV Capabilities Section 9.2.1.1.1 Configuring the VF BAR Mechanisms Section 9.2.1.2 VF Discovery Section 9.2.1.3 Function Dependency Lists Section 9.2.1.4 Interrupt Resource Allocation Section 9.2.2 SR-IOV Reset Mechanisms Section 9.2.2.1 SR-IOV Conventional Reset Section 9.2.2.2 FLR That Targets a VF Section 9.2.2.3 FLR That Targets a PF Section 9.2.3 IOV Re-initialization and Reallocation Section 9.3 Configuration Section 9.3.1 SR-IOV Configuration Overview Section 9.3.2 Configuration Space Section 9.3.3 SR-IOV Extended Capability Section 9.3.3.1 SR-IOV Extended Capability Header (Offset 00h) Section 9.3.3.2 SR-IOV Capabilities Register (04h) Section 9.3.3.2.1 VF Migration Capable Section 9.3.3.2.2 ARI Capable Hierarchy Preserved Section 9.3.3.2.3 VF Larger-Tag Requester Support Section 9.3.3.2.4 VF Migration Interrupt Message Number Section 9.3.3.3 SR-IOV Control Register (Offset 08h) Section 9.3.3.3.1 VF Enable Section 9.3.3.3.2 VF Migration Enable Section 9.3.3.3.3 VF Migration Interrupt Enable Section 9.3.3.3.4 VF MSE (Memory Space Enable) Section 9.3.3.3.5 ARI Capable Hierarchy Section 9.3.3.4 SR-IOV Status Register (Offset 0Ah) Section 9.3.3.4.1 VF Migration Status Section 9.3.3.5 InitialVFs (Offset 0Ch) Section 9.3.3.6 TotalVFs (Offset 0Eh) Section 9.3.3.7 NumVFs (Offset 10h) Section 9.3.3.8 Function Dependency Link (Offset 12h) Section 9.3.3.9 First VF Offset (Offset 14h) Section 9.3.3.10 VF Stride (Offset 16h) Section 9.3.3.11 VF Device ID (Offset 1Ah) Section 9.3.3.12 Supported Page Sizes (Offset 1Ch) Section 9.3.3.13 System Page Size (Offset 20h) Section 9.3.3.14 VF BAR0 (Offset 24h), VF BAR1 (Offset 28h), VF BAR2 (Offset 2Ch), VF BAR3 (Offset 30h), VF BAR4 (Offset 34h), VF BAR5 (Offset 38h) Section 9.3.3.15 VF Migration State Array Offset (Deprecated) (Offset 3Ch) Section 9.3.4 PF/VF Configuration Space Header Section 9.3.5 PCI Express Capability Changes Section 9.3.6 PCI Standard Capabilities Section 9.3.7 PCI Express Extended Capabilities Changes Chapter 10. Address Translation Services (ATS) Section 10.1 ATS Architectural Overview Section 10.1.1 Address Translation Services (ATS) Overview Section 10.1.2 Page Request Interface Extension Section 10.1.3 Process Address Space ID (PASID) Section 10.1.4 ATS Memory Attributes Section 10.2 ATS Translation Services Section 10.2.1 Memory Requests with Address Type Section 10.2.2 Translation Requests Section 10.2.2.1 Attribute Field Section 10.2.2.2 Length Field Section 10.2.2.3 Tag Field Section 10.2.2.4 Untranslated Address Field Section 10.2.2.5 No Write (NW) Flag Section 10.2.2.6 PASID on Translation Request Section 10.2.3 Translation Completion Section 10.2.3.1 Translated Address Field Section 10.2.3.2 Translation Range Size (S) Field Section 10.2.3.3 Non-snooped (N) Field Section 10.2.3.4 Untranslated Access Only (U) Field Section 10.2.3.5 Read (R) and Write (W) Fields Section 10.2.3.6 Execute Permitted (Exe) Section 10.2.3.7 Privileged Mode Access (Priv) Section 10.2.3.8 Global Mapping (Global) Section 10.2.3.9 ATS Memory Attributes Section 10.2.4 Completions with Multiple Translations Section 10.3 ATS Invalidation Section 10.3.1 Invalidate Request Section 10.3.2 Invalidate Completion Section 10.3.3 Invalidate Completion Semantics Section 10.3.4 Request Acceptance Rules Section 10.3.5 Invalidate Flow Control Section 10.3.6 Invalidate Ordering Semantics Section 10.3.7 Implicit Invalidation Events Section 10.3.8 PASID and Global Invalidate Section 10.4 Page Request Services Section 10.4.1 Page Request Message Section 10.4.1.1 PASID Usage Section 10.4.1.2 Managing PASID Usage on PRG Requests Section 10.4.1.2.1 Stop Marker Messages Section 10.4.2 Page Request Group Response Message Section 10.4.2.1 Response Code Field Section 10.4.2.2 PASID Usage on PRG Responses Section 10.5 ATS Configuration Section 10.5.1 ATS Extended Capability Section 10.5.1.1 ATS Extended Capability Header (Offset 00h) Section 10.5.1.2 ATS Capability Register (Offset 04h) Section 10.5.1.3 ATS Control Register (Offset 06h) Section 10.5.2 Page Request Extended Capability Structure Section 10.5.2.1 Page Request Extended Capability Header (Offset 00h) Section 10.5.2.2 Page Request Control Register (Offset 04h) Section 10.5.2.3 Page Request Status Register (Offset 06h) Section 10.5.2.4 Outstanding Page Request Capacity (Offset 08h) Section 10.5.2.5 Outstanding Page Request Allocation (Offset 0Ch) Appendix Appendix A. Isochronous Applications Section A.1 Introduction Section A.2 Isochronous Contract and Contract Parameters Section A.2.1 Isochronous Time Period and Isochronous Virtual Timeslot Section A.2.2 Isochronous Payload Size Section A.2.3 Isochronous Bandwidth Allocation Section A.2.4 Isochronous Transaction Latency Section A.2.5 An Example Illustrating Isochronous Parameters Section A.3 Isochronous Transaction Rules Section A.4 Transaction Ordering Section A.5 Isochronous Data Coherency Section A.6 Flow Control Section A.7 Considerations for Bandwidth Allocation Section A.7.1 Isochronous Bandwidth of PCI Express Links Section A.7.2 Isochronous Bandwidth of Endpoints Section A.7.3 Isochronous Bandwidth of Switches Section A.7.4 Isochronous Bandwidth of Root Complex Section A.8 Considerations for PCI Express Components Section A.8.1 An Endpoint as a Requester Section A.8.2 An Endpoint as a Completer Section A.8.3 Switches Section A.8.4 Root Complex Appendix B. Symbol Encoding Appendix C. Physical Layer Appendix Section C.1 8b/10b Data Scrambling Example Section C.2 128b/130b Data Scrambling Example Appendix D. Request Dependencies Appendix E. ID-Based Ordering Usage Section E.1 Introduction Section E.2 Potential Benefits with IDO Use Section E.2.1 Benefits for MFD/RP Direct Connect Section E.2.2 Benefits for Switched Environments Section E.2.3 Benefits for Integrated Endpoints Section E.2.4 IDO Use in Conjunction with RO Section E.3 When to Use IDO Section E.4 When Not to Use IDO Section E.4.1 When Not to Use IDO with Endpoints Section E.4.2 When Not to Use IDO with Root Ports Section E.5 Software Control of IDO Use Section E.5.1 Software Control of Endpoint IDO Use Section E.5.2 Software Control of Root Port IDO Use Appendix F. Message Code Usage Appendix G. Protocol Multiplexing Section G.1 Protocol Multiplexing Interactions with PCI Express Section G.2 PMUX Packets Section G.3 PMUX Packet Layout Section G.3.1 PMUX Packet Layout for 8b/10b Encoding Section G.3.2 PMUX Packet Layout at 128b/130b Encoding Section G.4 PMUX Control Section G.5 PMUX Extended Capability Section G.5.1 PMUX Extended Capability Header (Offset 00h) Section G.5.2 PMUX Capability Register (Offset 04h) Section G.5.3 PMUX Control Register (Offset 08h) Section G.5.4 PMUX Status Register (Offset 0Ch) Section G.5.5 PMUX Protocol Array (Offsets 10h through 48h) Appendix H. Flow Control Update Latency and ACK Update Latency Calculations Section H.1 Flow Control Update Latency Section H.2 Ack Latency Appendix I. Async Hot-Plug Reference Model Section I.1 Async Hot-Plug Initial Configuration Section I.2 Async Removal Configuration and Interrupt Handling Section I.3 Async Hot-Add Configuration and Interrupt Handling Appendix J. Alpha Power and Reverse lookup assignment Section J.1 Alpha Powers Section J.2 84 Byte to 86 Byte Encoder Section J.3 250 Byte to 256 Byte Encoder example Section J.4 86 Byte to 84 Byte Decoder Section J.5 256 Byte to 250 Byte decoder Appendix K. MATLAB created generator matrix for CRC code Section K.1 Generator Matrix output Section K.2 Flit 8 byte LCRC Appendix L. Example IDE TLP Acknowledgements