Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms

Description

This book guides the reader through the design of circuits and wireless IoT devices deployed in applications demanding low power, small size, and high levels of integration. The design of a sub-1V wireless-LAN receiver is detailed along with associated calibration algorithms. Some of the key circuits detailed include a successive approximation analog-to-digital converter, a rail-to-rail comparator, a digitally programmable CMOS low-noise amplifier, an RF voltage to current converter, and a fifth-order Chebyshev analog programmable filter. Helpful appendices are included teaching operational amplifier design, CMOS and SiGe low-noise amplifier design, impedance matching, noise and distortion analysis. While theory and design equations are presented throughout the book for the various circuit designs, practical implementation and design tradeoffs are emphasized so the reader can immediately apply knowledge gained. Receiver and calibration circuits are designed in a standard CMOS technology using a 900mV power supply. Provides readers with analytical tools and practical help, conveyed in a clear and concise manner, which will assist not only in understanding the material, but also in practical and functional implementation of the concepts demonstrated;Focuses on long range and broad-band IoT applications with a wireless-LAN focus, emphasizing detailed design techniques, helping readers transition from theoretical understanding to practical application;Bridges the gap between system level understanding and practical design implementation, providing readers with tools and techniques which can be applied immediately to their designs;Serves as a handy technical resource for practical design techniques, as well as a quick reference guide for design equations and examples pertinent to realistic applications. Preface References Contents About the Authors Chapter 1: Calibration Overview Chapter 2: SAR A/D Converter 2.1 SAR A/D Converter Implementation 2.2 Digital-to-Analog Converter Design Considerations 2.3 Rail-to-Rail Input Comparator 2.4 Low-Voltage Class AB Operational Amplifier Chapter 3: Calibration Filter 3.1 Programmable Filter Stage 3.2 Programmable Capacitor with Coarse and Fine Resolution 3.3 Fully Differential OPAMP with Common Mode Control Chapter 4: Clock Dividers 4.1 Reference Divider 4.2 Divide-by-40 Counter Chapter 5: Phase-Frequency Detector with No Dead Zone Chapter 6: Charge Pump with Four Programmable States Chapter 7: Fifth-Order Chebyshev Tunable Filter Chapter 8: Filter Calibration Results Chapter 9: WLAN Receiver Front End 9.1 RX-TX Switch 9.2 Low-Noise Amplifier 9.3 Voltage-to-Current Converter 9.4 Sampling Down-Converter 9.5 Trans-impedance Amplifier Chapter 10: WLAN Front-End Performance Appendices Appendix A: TIA Supplemental Analysis CMOS LNA Design Considerations Classical Two-Port Noise Model MOSFET LNA Noise Model Impedance Matching Gain Control Appendix C: Bipolar LNA Noise Optimization Bipolar Transistor Noise Model Bipolar Transistor Frequency Response Minimum Noise Figure Optimum Source Impedance Impedance Matching Linearity and Distortion Analysis Effects of Feedback on Distortion Appendix D: Folded Cascode OPAMP Design Foundry Process and Constants Slew Rate Input Stage Noise Analysis The Cascode Stage Class AB Output Stage Bias Circuits Appendix E: Thermometer Decoder (Topology) References Index