Deep Learning on Edge Computing Devices: Design Challenges of Algorithm and Architecture

Description

Deep Learning on Edge Computing Devices: Design Challenges of Algorithm and Architecture focuses on hardware architecture and embedded deep learning, including neural networks. The title helps researchers maximize the performance of Edge-deep learning models for mobile computing and other applications by presenting neural network algorithms and hardware design optimization approaches for Edge-deep learning. Applications are introduced in each section, and a comprehensive example, smart surveillance cameras, is presented at the end of the book, integrating innovation in both algorithm and hardware architecture. Structured into three parts, the book covers core concepts, theories and algorithms and architecture optimization. This book provides a solution for researchers looking to maximize the performance of deep learning models on Edge-computing devices through algorithm-hardware co-design. Front Cover Deep Learning on Edge Computing Devices Copyright Contents Preface Acknowledgements Part 1 Introduction 1 Introduction 1.1 Background 1.2 Applications and trends 1.3 Concepts and taxonomy 1.3.1 Preliminary concepts 1.3.2 Two stages of deep learning: training and inference 1.3.3 Cloud and edge devices 1.4 Challenges and objectives 1.5 Outline of the book References 2 The basics of deep learning 2.1 Feedforward neural networks 2.2 Deep neural networks 2.2.1 Convolutional neural networks 2.2.2 Recurrent neural networks 2.3 Learning objectives and training process 2.3.1 Loss function 2.3.2 Regularization 2.3.3 Gradient-based optimization method 2.4 Computational complexity References Part 2 Model and algorithm 3 Model design and compression 3.1 Background and challenges 3.2 Design of lightweight neural networks 3.2.1 SqueezeNet 3.2.2 MobileNet 3.2.3 ShuffleNet 3.2.4 EfficientNet 3.3 Model compression 3.3.1 Model pruning 3.3.2 Knowledge distillation References 4 Mix-precision model encoding and quantization 4.1 Background and challenges 4.2 Rate-distortion theory and sparse encoding 4.2.1 Rate-distortion theory 4.2.2 Activation quantization via bitwise bottleneck encoding 4.3 Bitwise bottleneck quantization methods 4.3.1 Neural network with bitwise bottlenecks 4.3.2 Training sparse bitwise bottlenecks 4.4 Application to efficient image classification 4.4.1 Experiment setting 4.4.2 Visualization and analysis 4.4.3 Comparison with the state-of-the-art approaches 4.4.4 Efficiency improvement References 5 Model encoding of binary neural networks 5.1 Background and challenges 5.2 The basic of binary neural network 5.3 The cellular binary neural network with lateral connections 5.3.1 Cellular binary neural network 5.3.2 Group sparse regularization 5.3.3 Loss function 5.3.4 Training process 5.4 Application to efficient image classification 5.4.1 Datasets and experiment settings 5.4.2 Ablation test 5.4.3 Experiments on ImageNet 5.4.4 Complexity analysis References Part 3 Architecture optimization 6 Binary neural network computing architecture 6.1 Background and challenges 6.2 Ensemble binary neural computing model 6.2.1 Convolutional neural network 6.2.2 Binary neural network 6.2.3 Ensemble binary neural network 6.3 Architecture design and optimization 6.3.1 Overall architecture 6.3.2 Architecture of computing array 6.3.3 Bagging processing element 6.4 Application of binary computing architecture 6.4.1 Experiment setting 6.4.2 Performance evaluation and comparison 6.4.3 Prototype system demonstration References 7 Algorithm and hardware codesign of sparse binary network on-chip 7.1 Background and challenges 7.2 Algorithm design and optimization 7.2.1 Deep belief network and restricted Boltzmann machine 7.2.2 Adaptive restricted Boltzmann machine 7.2.3 Training algorithm 7.2.4 Properties of the deep adaptive network 7.3 Near-memory computing architecture 7.4 Applications of deep adaptive network on chip 7.4.1 Experiment setting and measurements 7.4.2 MNIST handwritten images 7.4.3 Hyperspectral remote sensing images 7.4.4 Real-time analysis of video images References 8 Hardware architecture optimization for object tracking 8.1 Background and challenges 8.2 Algorithm 8.2.1 Object tracking algorithm 8.2.2 Memory optimization for spatiotemporal filtering 8.3 Hardware implementation and optimization 8.3.1 VLSI architecture 8.3.2 Block circuit design 8.4 Application experiments References 9 SensCamera: A learning-based smart camera prototype 9.1 Challenges beyond pattern recognition 9.2 Compressive convolutional network model 9.2.1 Standard compressive sensing 9.2.2 The framework of compressive convolutional network 9.2.3 Data embedding via convolution operation 9.2.4 Coherence regularization 9.3 Hardware implementation and optimization 9.4 Applications of SensCamera 9.4.1 Experiment setting 9.4.2 Performance of image compression 9.4.3 Performance of object detection 9.4.4 Performance of the SensCamera system References Index Back Cover