HDL Coder. User's Guide

Description

HDL Code Generation from MATLAB MATLAB Algorithm Design Functions Supported for HDL and SystemC Code Generation Supported MATLAB and Fixed Point Runtime Library Functions Fixed-Point Function Limitations Supported MATLAB Data Types, Operators, and Control Flow Statements Supported Data Types Supported Operators Control Flow Statements Persistent Variables and Persistent Array Variables Persistent Variables Persistent Array Variables Complex Data Type Support Declaring Complex Signals Conversion Between Complex and Real Signals Support for Vectors of Complex Numbers Complex Data Type Support for SystemC Code Generation Declaring Complex Signals Conversion Between Complex and Real Signals Support for Vectors of Complex Numbers HDL Code Generation for System Objects Why Use System Objects? Predefined System Objects User-Defined System Objects Limitations of HDL Code Generation for System Objects System object Examples for HDL Code Generation HDL Code Generation from System Objects HDL Code Generation for Streaming Matrix Inverse System Object HDL Code Generation for Streaming Matrix Multiply System Object HDL Code Generation from hdl.RAM System Object HDL Code Generation from A Non-Restoring Square Root System Object HDL Code Generation from Viterbi Decoder System Object Predefined System Objects Supported for HDL Code Generation Predefined System Objects in MATLAB Code Predefined System Objects in the MATLAB System Block Load constants from a MAT-File Generate Code for User-Defined System Objects How To Create A User-Defined System object User-Defined System object Example Map Matrices to ROM Model State with Persistent Variables and System Objects Bitwise Operations in MATLAB for HDL and SystemC Code Generation Bit Shifting and Rotation Bit Slicing and Bit Concatenation Mapping of Different Rounding and Overflow Methods from MATLAB to SystemC Guidelines for Writing MATLAB Code to Generate Efficient HDL and SystemC Code MATLAB Design Requirements for HDL and SystemC Code Generation Guidelines for Writing MATLAB Code For-Loop Best Practices for HDL Code Generation Monotonically Increasing Loop Counters Find Indices Using Loops Persistent Variables in Loops Persistent Arrays in Loops MATLAB Test Bench Requirements and Best Practices for Code Generation What Is a MATLAB Test Bench? MATLAB Test Bench Requirements MATLAB Test Bench Best Practices MATLAB to HDL Examples for Communications and Signal Processing Applications HDL Code Generation for LMS Filter Bisection Algorithm to Calculate Square Root of an Unsigned Fixed-Point Number Timing Offset Estimation Data Packetization Transmit and Receive FIFO Registers HDL Code Generation for Harris Corner Detection Algorithm HDL Code Generation for Adaptive Median Filter Contrast Adjustment Image Enhancement by Histogram Equalization HDL Code Generation for Image Format Conversion from RGB to YUV High Dynamic Range Imaging Accelerate Pixel-Streaming Designs Using MATLAB Coder Enhanced Edge Detection from Noisy Color Video Verify Sobel Edge Detection Algorithm in MATLAB-to-HDL Workflow MATLAB Best Practices and Design Patterns for HDL Code Generation Model a Counter for HDL and SystemC Code Generation MATLAB Code for the Counter Model a State Machine for HDL and SystemC Code Generation MATLAB Code for the Mealy State Machine MATLAB Code for the Moore State Machine Generate Hardware Instances For Local Functions MATLAB Local Functions MATLAB Code for mlhdlc_two_counters.m Implement RAM Using MATLAB Code Implement RAM Using a Persistent Array or System object Properties Implement RAM Using hdl.RAM Fixed-Point Conversion Specify Type Proposal Options Log Data for Histogram View and Modify Variable Information View Variable Information Modify Variable Information Revert Changes Promote Sim Min and Sim Max Values Automated Fixed-Point Conversion License Requirements Automated Fixed-Point Conversion Capabilities Code Coverage Proposing Data Types Locking Proposed Data Types Viewing Functions Viewing Variables Histogram Function Replacements Validating Types Testing Numerics Detecting Overflows Custom Plot Functions Edit Configuration Parameters for Fixed-Point Code Generation Create and Modify Configuration Objects Additional Functionalities Visualize Differences Between Floating-Point and Fixed-Point Results Inspecting Data Using the Simulation Data Inspector What Is the Simulation Data Inspector? Import Logged Data Export Logged Data Group Signals Run Options Create Report Comparison Options Enabling Plotting Using the Simulation Data Inspector Save and Load Simulation Data Inspector Sessions Enable Plotting Using the Simulation Data Inspector From the UI From the Command Line Replacing Functions Using Lookup Table Approximations Replace a Custom Function with a Lookup Table Using the HDL Coder App From the Command Line Replace the exp Function with a Lookup Table From the UI From the Command Line Data Type Issues in Generated Code Enable the Highlight Option in a Project Enable the Highlight Option at the Command Line Stowaway Doubles Stowaway Singles Expensive Fixed-Point Operations Working with Fixed-Point Code Floating-Point to Fixed-Point Conversion Fixed-Point Type Conversion and Refinement Working with Generated Fixed-Point Files Fixed-Point Type Conversion and Derived Ranges Generate HDL-Compatible Lookup Table Function Replacements Using coder.approximate Code Generation Create and Set Up Your Project Create a New Project Open an Existing Project Add Files to the Project Specify Properties of Entry-Point Function Inputs When to Specify Input Properties Why You Must Specify Input Properties Properties to Specify Rules for Specifying Properties of Primary Inputs Methods for Defining Properties of Primary Inputs Code Generation Reports Report Generation Report Location Errors and Warnings Files and Functions MATLAB Source MATLAB Variables Additional Reports Report Limitations Generate Instantiable Code for Functions How to Generate Instantiable Code for Functions Generate Code Inline for Specific Functions Limitations for Instantiable Code Generation for Functions Edit Configuration Parameters for HDL Coder Create and Modify Configuration Objects Additional Functionalities Integrate Custom HDL Code Into MATLAB Design Define the hdl.BlackBox System object Use System object In MATLAB Design Function Generate HDL Code Limitations for hdl.BlackBox Enable MATLAB Function Block Generation Requirements for MATLAB Function Block Generation Enable MATLAB Function Block Generation Restrictions for MATLAB Function Block Generation Results of MATLAB Function Block Generation System Design with HDL Code Generation from MATLAB and Simulink Specify the Clock Enable Rate Why Specify the Clock Enable Rate? How to Specify the Clock Enable Rate Specify Test Bench Clock Enable Toggle Rate When to Specify Test Bench Clock Enable Toggle Rate How to Specify Test Bench Clock Enable Toggle Rate Generate an HDL Coding Standard Report from MATLAB Using the HDL Workflow Advisor Using the Command Line Generate an HDL Lint Tool Script How To Generate an HDL Lint Tool Script Generate HDL Code from MATLAB Functions that Use Automated Lookup Table Generation Generate Board-Independent IP Core from MATLAB Algorithm Requirements and Limitations for IP Core Generation Generate Board-Independent IP Core Minimize Clock Enables Using the GUI Using the Command Line Limitations Verification Verify Code with HDL Test Bench Test Bench Generation How Test Bench Generation Works Test Bench Data Files Test Bench Data Type Limitations Use Constants Instead of File I/O Deployment Generate Synthesis Scripts Optimization Map Matrices to Block RAMs to Reduce Area Map Persistent Arrays and dsp.Delay Objects to RAM Enable RAM Mapping RAM Mapping Requirements for Persistent Arrays and System object Properties RAM Mapping Requirements for dsp.Delay System Objects RAM Mapping Comparison Pipelining MATLAB Code Port Registers Input and Output Pipeline Registers Operation Pipelining Pipeline MATLAB Expressions How To Pipeline a MATLAB Expression Limitations of Pipelining for MATLAB Expressions Distributed Pipelining What is Distributed Pipelining? Benefits and Costs of Distributed Pipelining Selected Bibliography Distributed Pipelining for Clock Speed Optimization Optimize Clock Speed for MATLAB Code by Using Adaptive Pipelining Optimize Feedback Loop Design and Maintain High Data Precision for HDL Code Generation Optimize MATLAB Loops Loop Streaming Loop Unrolling How to Optimize MATLAB Loops Limitations for MATLAB Loop Optimization Constant Multiplier Optimization What is Constant Multiplier Optimization? Specify Constant Multiplier Optimization Resource Sharing of Multipliers to Reduce Area Loop Streaming to Reduce Area Constant Multiplier Optimization to Reduce Area HDL Workflow Advisor Reference HDL Workflow Advisor Overview MATLAB to HDL Code and Synthesis MATLAB to HDL Code Conversion Code Generation: Target Tab Code Generation: Coding Style Tab Code Generation: Clocks and Ports Tab Code Generation: Test Bench Tab Code Generation: Optimizations Tab Simulation and Verification Synthesis and Analysis SystemC Code Generation from MATLAB MATLAB to SystemC Examples for Communications and Signal Processing Applications SystemC Code Generation for LMS Filter SystemC Code Generation for Bisection Algorithm SystemC Code Generation for Data Packetization SystemC Code Generation for DF2T Filter SystemC Code Generation For Transmit and Receive FIFO Registers SystemC Code Generation for Contrast Adjustment SystemC Code Generation for Image Format Conversion from RGB to YUV SystemC Code Generation for Advanced Encryption Standard SystemC Code Generation Get Started with MATLAB to SystemC Workflow Using HDL Coder App Get Started with MATLAB to SystemC Workflow Using the Command Line Interface Replace Arithmetic Operation to Generate Efficient SystemC Code Verification Verify SystemC Code That Has an HDL Test Bench MATLAB to SystemC Code Conversion Options MATLAB to SystemC Code Conversion SystemC Code Generation: Target Tab SystemC Code Generation: Coding Style Tab SystemC Code Generation: Optimizations Tab SystemC Optimizations Map Persistent Arrays to RAM Enable RAM Mapping RAM Mapping Requirements for Persistent Arrays Pipelining of for-Loops Issues with Pipelined for-Loops Map Persistent Variables to RAM for Histogram Equalization HDL Code Generation from Simulink Model Design for HDL Code Generation Signal and Data Type Support Buses Enumerations Matrices Unsupported Signal and Data Types Use Simulink Templates for HDL Code Generation Create Model Using HDL Coder Model Template HDL Coder Model Templates Generate DUT Ports for Tunable Parameters Prerequisites Create and Add Tunable Parameter That Maps to DUT Ports Generated Code Limitations Use Tunable Parameter in Other Blocks Generate Parameterized Code for Referenced Models Parameterize Referenced Model for HDL Code Generation Restrictions Generating HDL Code for Subsystems with Array of Buses How HDL Coder Generates Code for Array of Buses Array of Buses Limitations Generate VHDL Code with Record Types for Bus Signals Requirements and Considerations Use Record Types for Bus in HDL Code Generation Generate Record Types for Bus Signals at Subsystem Interface Generate Record Types for Array of Bus Limitations Implement Control Signal-Based Mathematical Functions by Using HDL Coder Implement Sqrt Block With Control Signals Implement Reciprocal Block With Control Signals Implement rSqrt Block With Control Signals Implement Divide Block With Control Signals Implement Sine and Cosine Block With Control Signals Implement Atan2 Block With Control Signals Using ForEach Subsystems in HDL Coder Generate HDL Code for Blocks Inside For Each Subsystem Field-Oriented Control of a Permanent Magnet Synchronous Machine Model and Debug Test Point Signals with HDL Coder Allocate Sufficient Delays for Floating-Point Operations Problem Cause Solution Optimize Generated HDL Code for Multirate Designs with Large Rate Differentials Issue Description Recommendations Getting Started with HDL Coder Native Floating-Point Support Key Features Numeric Considerations and IEEE-754 Standard Compliance Floating Point Types Data Type Considerations Numeric Considerations for Native Floating-Point Nearest Even Digit Rounding Denormal Numbers Exception Handling Relative Accuracy and ULP Considerations ULP Considerations of Native Floating-Point Operators Adherence of Native Floating Point Operators to IEEE-754 Standard ULP Values of Floating Point Operators Considerations Latency Values of Floating-Point Operators Math Operations Trigonometric Operations Comparisons and Conversions Latency Considerations with Native Floating Point Generate Target-Independent HDL Code with Native Floating-Point How HDL Coder Generates Target-Independent HDL Code Enable Native Floating Point and Generate Code View Code Generation Report Analyze Results Limitation Floating Point Support: Field-Oriented Control Algorithm Design Model by Using HDL Coder Native Floating Point and Intel Hard Floating Point Verify the Generated Code from Native Floating-Point Specify the Tolerance Strategy Verify the Generated Code with HDL Test Bench Verify the Generated Code with Cosimulation Limitation Simulink Blocks Supported by Using Native Floating Point HDL Floating Point Operations Library Supported Simulink Blocks in Math Operations Library Supported Functions in Math Function Block Supported Simulink Blocks in Other Libraries Simulink Block Restrictions Synthesis Benchmark of Common Native Floating Point Operators Supported Data Types and Scope Supported Data Types Unsupported Data Types Scope for Variables Import Verilog Code and Generate Simulink Model HDL Import HDL Import Requirements Import HDL Code Model Location Errors and Warnings Limitations of Verilog HDL Import Supported Verilog Constructs for HDL Import Module Definition and Instantiations Data Types and Vectors Identifiers and Comments Assignments Operators Conditional and Looping Statements Procedural Blocks and Events Other Constructs Verilog Dataflow Modeling with HDL Import Supported Verilog Dataflow Patterns Unsupported Verilog Dataflow Patterns Simulate and Generate HDL Code for the Float Typecast Block Generate Simulink Model From CORDIC Atan2 Verilog Code Simulink to HDL Examples for Communication and Signal Processing Applications Programmable FIR Filter for FPGA Multichannel FIR Filter for FPGA High-Throughput Channelizer for FPGA Implement Digital Downconverter for FPGA Implement Digital Upconverter for FPGA HDL QAM Transmitter and Receiver Airplane Tracking with ADS-B Captured Data HDL Code Generation for Viterbi Decoder Design Video Processing Algorithms for HDL in Simulink Edge Detection and Image Overlay Lane Detection HDL QPSK Transmitter and Receiver Code Generation Options in the HDL Coder Dialog Boxes Set HDL Code Generation Options HDL Code Generation Options in the Configuration Parameters Dialog Box HDL Code Tab in Simulink Toolstrip HDL Code Options in the Block Context Menu The HDL Block Properties Dialog Box HDL Code Generation Options in Configuration Parameters Dialog Box HDL Code Generation Pane: Target HDL Code Generation Pane: Optimization HDL Code Generation Pane: Floating Point HDL Code Generation Pane: Global Settings HDL Code Generation Pane: Report HDL Code Generation Pane: Testbench HDL Code Generation Pane: EDA Tool Scripts Generate HDL Code from Simulink Model Using Configuration Parameters FIR Filter Model Create a Folder and Copy Relevant Files Open HDL Code Generation Pane of Configuration Parameters Dialog Box Generate HDL Code Generate HDL Code from Simulink Model from Command Line FIR Filter Model Create a Folder and Copy Relevant Files Generate HDL Code HDL Code Generation Pane: General HDL Code Generation Top-Level Pane Overview Buttons in the HDL Code Generation Top-Level Pane Target Language and Folder Selection Parameters Generate HDL for Language Folder Restore Model Defaults Run Compatibility Checker Generate HDL Code Generation Pane: Target Target Overview Tool and Device Parameters Synthesis Tool Family Device Package Speed Target Frequency Parameter Settings Command-Line Information See Also HDL Code Generation Pane: Optimization Optimization Overview General Optimization Parameters Transform non zero initial value delay Remove Unused Ports Balance delays RAM Mapping Parameters Map pipeline delays to RAM RAM mapping threshold Pipelining Parameters Clock-rate pipelining Allow clock-rate pipelining of DUT output ports Balance clock-rate pipelined DUT output ports Distributed pipelining Distributed pipelining priority Preserve design delays Use synthesis estimates for distributed pipelining Adaptive pipelining Map lookup tables to RAM Resource Sharing Parameters for Adders and Multipliers Share Adders Adder sharing minimum bitwidth Share Multipliers Multiplier sharing minimum bitwidth Multiplier promotion threshold Multiplier partitioning threshold Share Multiply-Add blocks Multiply-Add block sharing minimum bitwidth Resource Sharing Parameters for Subsystems and Floating-Point IPs Share Atomic subsystems Share MATLAB Function blocks Share Floating-Point IPs Multicycle Path Constraints Parameters Enable-based constraints Register-to-register path info Frame to Sample Conversion Parameters Enable frame to sample conversion Samples per cycle Input FIFO size Output FIFO size Input processing order Delay size threshold for external memory HDL Code Generation Pane: Floating Point Floating Point Overview Floating Point IP Library Parameters Use Floating Point Vendor Specific Floating Point Library Native Floating-Point Parameters Latency Strategy Handle Denormals Mantissa Multiplier Strategy FPGA Floating-Point Library Targeting Properties Initialize IP Pipelines To Zero Latency Strategy Objective IP Settings HDL Code Generation Pane: Global Settings Global Settings Overview Clock Settings and Timing Controller Postfix Parameters Clock input port Clock inputs Clock edge Clocked process postfix Timing controller postfix Reset Settings and Parameters Reset type Reset asserted level Reset input port Clock Enable Settings and Parameters Clock enable input port Enable prefix Oversampling factor Settings Dependency Command-Line Information See Also Comment in header Settings Command-Line Information See Also Language-Specific File Extension Parameters Verilog file extension VHDL file extension Language-Specific Identifiers and Postfix Parameters Entity conflict postfix Package postfix Reserved word postfix Module name prefix Pipeline postfix Split entity and architecture Parameters Split entity file postfix Split arch file postfix Split entity and architecture Complex Signals Postfix Parameters Complex real part postfix Complex imaginary part postfix VHDL Architecture and Library Name and Code for Model Reference Parameters VHDL architecture name VHDL library name Generate VHDL code for model references into a single library Generate Statement and Vector and Component Instance Label Parameters Block generate label Output generate label Instance generate label Vector prefix Instance postfix Instance prefix Dependency Map file postfix Input and Output Port and Clock Enable Output Type Parameters Input data type Output data type Clock Enable output port Minimize Clock Enables and Reset Signal Parameters Minimize clock enables Minimize global resets DUT Port Configuration Parameters Use trigger signal as clock Enable HDL DUT port generation for tunable parameters Balance delays for generated DUT input ports Enable HDL DUT port generation for test points Balance delays for generated DUT output ports Scalarize ports Max number of I/O pins for FPGA deployment Check for DUT pin count exceeding I/O Threshold RTL Annotation Parameters Use Verilog `timescale directives Verilog timescale specification Code Reuse Inline VHDL configuration Concatenate type safe zeros Generate obfuscated HDL code RTL Customization Parameters for Constants and MATLAB Function Blocks Inline MATLAB Function block code Represent constant values by aggregates RTL Customization Parameters for RAMs Initialize all RAM blocks RAM Architecture No-reset registers initialization Settings Usage Notes Command-Line Information See Also RTL Style Parameters Use “rising_edge/falling_edge” Style for Registers Minimize Intermediate Signals Unroll For-Generate Loops in VHDL Code Generate Parameterized HDL Code from Masked Subsystem Enumerated Type Encoding Scheme Indexing for Scalarized Port Naming Generate Record Types for Bus Timing Controller Settings Optimize timing controller Timing controller architecture File Comment Customization Parameters Enable Comments Include Requirements in Block Comments Emit Time/Date Stamp in Header Custom File Header Comment Custom File Footer Comment Choose Coding Standard and Report Option Parameters HDL coding standard Show passing rules in coding standard report Basic Coding Practices Parameters Check for duplicate names Check for HDL keywords in design names Check module, instance, entity name length Check signal, port, and parameter name length RTL Description Rules for clock enables and resets Parameters Check for clock enable signals Detect usage of reset signals Detect usage of asynchronous reset signals RTL Description Rules for Conditional Parameters Check for conditional statements in processes Check for assignments to the same variable in multiple cascaded control regions Check if-else statement chain length Check if-else statement nesting depth Other RTL Description Rule Parameters Minimize use of variables Check for initial statements that set RAM initial values Check multiplier width RTL Design Rule Parameters Check for non-integer constants Check line length Model Generation Parameters for HDL Code Generated model Validation model Naming and Layout Options for Model Generation Prefix for generated model name Suffix for validation model name Layout Style Auto signal routing Inter-block horizontal scaling Inter-block vertical scaling Diagnostic Parameters for Optimizations Highlight feedback loops inhibiting delay balancing and optimizations Highlight blocks inhibiting clock-rate pipelining Highlight blocks inhibiting distributed pipelining Highlight lookup tables mapped to RAM Highlight dead blocks removed in generated code Diagnostic Parameters for Reals and Black Box Interfaces Check for name conflicts in black box interfaces Check for presence of reals in generated HDL code Check for presence of unbalanced delays in generated HDL code Code Generation Output Parameter Generate HDL code Suppress out of bounds access errors by generating simulation-only index checks HDL Code Generation Pane: Report Report Pane Overview See Also Code Generation Report Parameters Generate traceability report Traceability style Generate model Web view Generate resource utilization report Generate high-level timing critical path report Generate optimization report Custom Timing Database Directory HDL Code Generation Pane: Test Bench Test Bench Overview Generate Test Bench Button Test Bench Generation Output Parameters HDL test bench Cosimulation model SystemVerilog DPI test bench Simulation tool HDL code coverage Test Bench Postfix Parameters Test bench name postfix Test bench reference postfix Test bench data file name postfix Clock and Reset Input Parameters for Testbench Force clock Clock high time (ns) Clock low time (ns) Force clock enable Clock enable delay (in clock cycles) Force reset Reset length (in clock cycles) Setup and Hold Time Parameters for Testbench Hold time (ns) Setup time (ns) Test Bench Stimulus and Output Parameters Hold input data between samples Initialize test bench inputs Ignore output data checking (number of samples) Use file I/O to read/write test bench data Multi-File Testbench and Simulation Library Path Parameters Multi-file test bench Simulation library path Floating-Point Tolerance Parameters Floating point tolerance check based on Tolerance Value HDL Code Generation Pane: EDA Tool Scripts EDA Tool Scripts Overview Generate EDA scripts Settings Command-Line Information See Also Compilation Script Parameters Compile file postfix Compile initialization Compile command for VHDL Compile command for Verilog Compile termination Simulation Script Parameters Simulation file postfix Simulation initialization Simulation command Simulation waveform viewing command Simulation termination Simulator flags Synthesis Script Parameters Choose synthesis tool Synthesis file postfix Synthesis initialization Synthesis command Synthesis termination Additional files to add to synthesis project Lint Script Parameters Choose HDL lint tool Lint initialization Lint command Lint termination Modeling Guidelines HDL Modeling Guidelines Severity Levels Model Design and Compatibility Guidelines - By Numbered List Guidelines 1.1: Basic Settings Guidelines 1.2: DUT Subsystem and Hierarchical Modeling Guidelines 1.3: Vectors, Matrices, and Buses Guidelines 1.4: Clock Bundle Signals Guidelines 1.5: Native Floating Point Guidelines for Supported Blocks and Data Types - By Numbered List Guidelines 2.1: HDL RAMs and HDL Operations Library Guidelines 2.2: Logic and Bit Operations Library Guidelines 2.3: Lookup Table and Signal Routing Blocks Guidelines 2.4: Ports and Subsystems Guideline 2.5: Rate Change and Constant Blocks Guideline 2.6: Delay Blocks Guideline 2.7: Multiplication and Accumulation Operations Guideline 2.8: MATLAB Function Blocks Guideline 2.9: Stateflow Charts Guidelines 2.10: Data Types Guidelines for Speed and Area Optimizations - By Numbered List Guidelines 3.1: Resource Sharing and Streaming Guidelines 3.2: Clock Rate Pipelining and Distributed Pipelining Basic Guidelines for Modeling HDL Algorithm in Simulink Use HDL-Supported Blocks Partition Model into DUT and Test Bench Avoid Using Double-Byte Characters Document Model Features and Attributes Guidelines for Model Setup and Checking Model Compatibility Customize hdlsetup Function Based on Target Application Check Subsystem for HDL Compatibility Run Model Checks for HDL Coder Modeling with Simulink, Stateflow, and MATLAB Function Blocks Guideline ID Severity Description Terminate Unconnected Block Outputs and Usage of Commenting Blocks Terminate Unconnected Block Outputs Using Comment Out and Comment Through of Blocks Identify and Programmatically Change and Display HDL Block Parameters Adjust Sizes of Constant and Gain Blocks for Identifying Parameters Display Parameters That Affect HDL Code Generation Change Block Parameters by Using find_system and set_param DUT Subsystem Guidelines DUT Subsystem Considerations Convert DUT Subsystem to Model Reference for Testbenches with Continuous Blocks Insert Handwritten Code into Simulink Modeling Environment Hierarchical Modeling Guidelines Avoid Constant Block Connections to Subsystem Port Boundaries Generate Parameterized HDL Code for Constant and Gain Blocks Place Physical Signal Lines Inside a Subsystem Design Considerations for Matrices and Vectors Modeling Requirements for Matrices Avoid Generating Ascending Bit Order in HDL Code From Vector Signals Use Bus Signals to Improve Readability of Model and Generate HDL Code Guidelines for Clock and Reset Signals Use Global Oversampling to Create Frequency-Divided Clock Create Multirate Model with Integer Clock Multiples by Clock Division Use Dual Rate Dual Port RAM for Noninteger Multiple Sample Times Asynchronous Clock Modeling in HDL Coder Use Global Reset Type Setting Based on Target Hardware Modeling with Native Floating Point Guideline ID Severity Description Design Considerations for RAM Blocks and Blocks in HDL Operations Library RAM Block Access Considerations Serial to Parallel Conversion Usage of Blocks in Logic and Bit Operations Library Logical and Arithmetic Bit Shift Operations Usage of Logical Operator, Bitwise Operator, and Bit Reduce Blocks Use Boolean Output for Compare to Constant and Relational Operator Blocks Generate FPGA Block RAM from Lookup Tables Recommended Block Parameter Settings of Multiport Switch Block for Numeric and Enumerated Types Usage of Different Subsystem Types Virtual Subsystem: Use as DUT Atomic and Virtual Subsystems: Generate Reusable HDL Files Variant Subsystem: Using Variant Subsystems for HDL Code Generation Model References: Build Model Design Using Smaller Partitions Block Settings of Enabled and Triggered Subsystems Usage of Rate Change and Constant Blocks Usage of Rate Conversion Blocks Use Discrete and Finite Sample Time for Constant Block Guidelines for Using Delays and Goto and From Blocks for HDL Code Generation Appropriate Usage of Delay Blocks as Registers Absorb Delays to Avoid Timing Difference Map Large Delays to Block RAM Required HDL Settings for Goto and From Blocks Modeling Efficient Multiplication and Division Operations for FPGA Targeting Designing Multipliers and Adders for Efficient Mapping to DSP Blocks on FPGA Set ConstMultiplierOptimization HDL Block Property to auto for Gain Block Use ShiftAdd Architecture of Divide Block for Fixed-Point Types Using Persistent Variables and fi Objects Inside MATLAB Function Blocks for HDL Code Generation Update Persistent Variables at End of MATLAB Function Avoid Algebraic Loop Errors from Persistent Variables inside MATLAB Function Blocks Use hdlfimath Setting and Specify fi Objects inside MATLAB Function Block Guidelines for HDL Code Generation Using Stateflow Charts Choose State Machine Type based on HDL Implementation Requirements Specify Block Configuration Settings of Stateflow Chart Insert Unconditional Transition State for Else Statement in HDL Code Data Type Settings and Casting in Stateflow Chart for HDL Code Generation Using Absolute Time Temporal Logic in Stateflow Charts Modeling Error (default) State in Stateflow Charts Enable Clock-Driven Outputs of Stateflow Charts (Moore Charts Only) Enumeration type for active state monitoring in a Stateflow chart with no default value Simulink Data Type Considerations Use Boolean for Logical Data and Ufix1 for Numerical Data Specify Data Type of Gain Blocks Enumerated Data Type Restrictions Resource Sharing Settings for Various Blocks Resource Sharing of Add Blocks Resource Sharing of Gain Blocks Resource Sharing of Product Blocks Resource Sharing of Multiply-Add Blocks Resource Sharing of Subsystems and Floating-Point IPs General Considerations for Sharing of Subsystems Use MATLAB Datapath Architecture for Sharing with MATLAB Function Blocks Sharing of Subsystems Resource Sharing of Floating-Point IPs Resource Sharing Guidelines for Vector Processing and Matrix Multiplication Use StreamingFactor for Resource Sharing of Vector Signals Use SharingFactor and HDL Block Properties for Sharing Matrix Multiplication Operations Distributed Pipelining and Clock-Rate Pipelining Guidelines Clock-Rate Pipelining Guidelines Recommended Distributed Pipelining Settings Insert Distributed Pipeline Registers for Blocks with Vector Data Type Inputs Guideline ID Severity Description Supported Blocks Library and Block Properties View HDL-Supported Blocks and HDL-Specific Block Documentation View HDL-Supported Blocks and Documentation View HDL-Specific Block Documentation HDL Block Properties: General Overview AdaptivePipelining BalanceDelays ClockRatePipelining CodingStyle ConstMultiplierOptimization ConstrainedOutputPipeline DistributedPipelining DotProductStrategy DSPStyle FlattenHierarchy GuardIndexVariables InputPipeline InstantiateFunctions InstantiateStages LoopOptimization LUTRegisterResetType MapPersistentVarsToRAM MapToRAM OutputPipeline PreserveUpstreamLogic RAMDirective ResetType SerialPartition SharingFactor SoftReset StreamingFactor UsePipelines UseRAM VariablesToPipeline HDL Block Properties: Native Floating Point Overview CheckResetToZero DivisionAlgorithm HandleDenormals InputRangeReduction LatencyStrategy CustomLatency NFPCustomLatency MantissaMultiplyStrategy MaxIterations HDL Filter Block Properties AdderTreePipeline AddPipelineRegisters ChannelSharing CoeffMultipliers DALUTPartition DARadix FoldingFactor MultiplierInputPipeline MultiplierOutputPipeline NumMultipliers ReuseAccum SerialPartition HDL Filter Architectures Fully Parallel Architecture Serial Architectures Frame-Based Architecture Distributed Arithmetic for HDL Filters Requirements and Considerations for Generating Distributed Arithmetic Code Further References Set and View HDL Model and Block Parameters Set HDL Block Parameters Set HDL Block Parameters for Multiple Blocks Programmatically View All HDL Block Parameters View Non-Default HDL Block Parameters View HDL Model Parameters Pass through, No HDL, and Cascade Implementations Pass-through and No HDL Implementations Cascade Architecture Best Practices Build a ROM Block with Simulink Blocks Getting Started with RAM and ROM in Simulink Wireless Communications Design for ASICs, FPGAs, and SoCs From Mathematical Algorithm to Hardware Implementation HDL-Optimized Blocks Reference Applications Generate HDL Code and Prototype on FPGA Generating HDL Code for Multirate Models Code Generation from Multirate Models Clock Enable Generation for a Multirate DUT Timing Controller for Multirate Models Timing Controller Naming Generate Reset for Timing Controller Requirements for Timing Controller Reset Port Generation How To Generate Reset for Timing Controller Limitations for Timing Controller Reset Port Generation Multirate Model Requirements for HDL Code Generation Model Configuration Parameters Sample Rate Blocks To Use For Rate Transitions Generate a Global Oversampling Clock Why Use a Global Oversampling Clock? Requirements for the Oversampling Factor Specifying the Oversampling Factor From the GUI Specifying the Oversampling Factor From the Command Line Resolving Oversampling Rate Conflicts Using Multiple Clocks in HDL Coder Using Triggered Subsystems for HDL Code Generation Best Practices Using the Signal Editor Block Using Trigger As Clock Specify Trigger As Clock Trigger As Clock Without Synchronous Registers Model Trigger Signal As Clock in Triggered Subsystem Use Triggered and Resettable Subsystem to Model Clock and Reset Signals Model Single Clock and Reset Signal Using Triggered and Resettable Subsystems Limitations Use Triggered Subsystem for Asynchronous Clock Domain Generate Multiple Clocks Using Trigger As Clock Generate Multiple Clocks and Resets Using Triggered and Resettable Subsystems Generate Multicycle Path Information Files Overview Format and Content of a Multicycle Path Information File File Naming and Location Conventions Generating Multicycle Path Information Files Using the GUI Generating Multicycle Path Information Files Using the Command Line Limitations Meet Timing Requirements Using Enable-Based Multicycle Path Constraints How Enable-Based Multicycle Path Constraints Work Specify Enable-Based Constraints Benefits of Using Enable-Based Constraints Modeling Guidelines Multicycle Path Constraints for Various Synthesis Tools Preserve Enable Signals in Timing Control Logic Limitations Use Multicycle Path Constraints to Meet Timing for Slow Paths Optimization Speed and Area Optimizations in HDL Coder Optimizations in MATLAB HDL Code Generation Optimizations in Simulink HDL Code Generation General Optimizations Speed Optimizations Area Optimizations Automatic Iterative Optimization How Automatic Iterative Optimization Works Automatic Iterative Optimization Output Automatic Iterative Optimization Report Automatic Iterative Optimization Synthesis Tool and Hardware Limitations of Automatic Iterative Optimization Generated Model and Validation Model Generated Model Validation Model Locate Numeric Differences After Speed Optimization Simplify Constant Operations and Reduce Design Complexity in HDL Coder Optimization with Constrained Overclocking Why Constrain Overclocking? Optimizations that Overclock Resources How to Use Constrained Overclocking Constrained Overclocking Limitations Resolve Numeric Mismatch with Delay Balancing Resolve Simulation Mismatch when Pipelining with a Feedback Loop Outside the DUT Streaming What Is Streaming? Specify Streaming How to Determine Streaming Factor and Sample Time Determine Blocks That Support Streaming Requirements for Streaming Subsystems Streaming Report Resource Sharing How Resource Sharing Works Benefits and Costs of Resource Sharing Shareable Resources in Different Blocks Specify Resource Sharing Limitations for Resource Sharing Block Requirements for Resource Sharing Resource Sharing Report Streaming: Area Optimization Resource Sharing for Area Optimization Single-Rate Resource Sharing Architecture Improve Resource Sharing with Design Modifications Improve Resource Sharing with Clone Detection and Replacement Delay Balancing Specify Delay Balancing Delay Balancing Considerations Delay Absorption During Delay Balancing Delay Balancing Limitations Delay Balancing Report Use Delay Absorption While Modeling with Latency Delay Balancing and Validation Model Workflow in HDL Coder Control the Scope of Delay Balancing Delay Balancing on Multirate Designs Find Feedback Loops Specify Highlighting of Feedback Loops Remove Highlighting Limitations Hierarchy Flattening What Is Hierarchy Flattening? When to Flatten Hierarchy Considerations How to Flatten Hierarchy Limitations for Hierarchy Flattening Hierarchy Flattening Report Apply RAM Mapping to Optimize Area RAM Mapping for a Simulink Model RAM Mapping for a MATLAB Design Use the RAM Mapping Threshold Exclude Inefficient RAM Mapping RAM Mapping With the MATLAB Function Block Distributed Pipelining What Is Distributed Pipelining? Benefits and Costs of Distributed Pipelining How Distributed Pipelining Works Requirements for Distributed Pipelining Specify Distributed Pipelining Limitations of Distributed Pipelining Distributed Pipelining Report Selected Bibliography Distributed Pipelining Using Synthesis Timing Estimates Synthesis Timing Estimates in Distributed Pipelining How Distributed Pipelining Works By Using Synthesis Timing Estimates Requirements for Synthesis Timing Estimates for Distributed Pipelining Specify Distributed Pipelining to Use Synthesis Timing Estimates Limitations Distributed Pipelining: Speed Optimization Constrained Output Pipelining What Is Constrained Output Pipelining? When to Use Constrained Output Pipelining Requirements for Constrained Output Pipelining Specify Constrained Output Pipelining Limitations of Constrained Output Pipelining Clock-Rate Pipelining Rationale for Clock-Rate Pipelining How Clock-Rate Pipelining Works in a Simulink Model How Clock-Rate Pipelining Works in a MATLAB Function Clock-Rate Pipelining and Hierarchy Flattening Clock-Rate Pipelining for DUT Output Ports Specify Clock-Rate Pipelining Limitations for Clock-Rate Pipelining Increase Clock Frequency Using Clock-Rate Pipelining Iteratively Maximize Clock Frequency by Using Speed Optimizations Adaptive Pipelining Requirements Specify Adaptive Pipelining Supported Blocks Pipeline Insertion for Rate Transition and Downsample Blocks Pipeline Insertion for Product and Gain Blocks Pipeline Insertion for Multiply-Add and Multiply-Accumulate Blocks Pipeline Insertion for MATLAB Function Blocks Adaptive Pipelining Report Design Patterns That Require Adaptive Pipelining Audio System That Uses Low Pass, Band Pass, and High Pass Filters Discrete FIR Filter That Uses Resource Sharing Critical Path Estimation Without Running Synthesis Critical Path Estimation Process Use Critical Path Estimation Characterized Blocks Considerations HDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture Subsystem Optimizations for Filters Sharing Streaming Pipelining Area Reduction of Multichannel Filter Subsystem Area Reduction of Filter Subsystem Remove Redundant Logic and Unused Blocks in Generated HDL Code Optimize Unconnected Ports in HDL Code for Simulink Models I/O Optimizations HDL Code Generation from Frame-Based Algorithms Generating HDL Code from a Frame-based Algorithm Specify the Frame-to-Sample Conversion Optimization Generate HDL Code from a Frame-Based Model Example Hardware Considerations Supported Blocks and Operations Limitations Use Neighborhood, Reduction, and Iterator Patterns with a Frame-Based Model or Function for HDL Code Generation Generate HDL Code from Frame-Based Models by Using Neighborhood Modeling Methods Use Sample-Based Inputs and Frame-Based Inputs in an Algorithm Synthesize Code for Frame-Based Model Offload Large Delays from Frame-Based Models to External Memory Deploy Frame-Based Models with AXI4-Stream Video Interfaces in Zynq-Based Hardware Optimize Area Usage For Frame-Based Algorithms with Tall Array Inputs Compute Image Characteristics with a Frame-Based Model for HDL Code Generation Code Generation Reports, HDL Compatibility Checker, Block Support Library, and Code Annotation Create and Use Code Generation Reports Report Generation Code Generation Report Timing and Area Report Optimization Report Navigate Between Simulink Model and HDL Code by Using Traceability How Traceability Works Generate Traceability Report Report Location View the Traceability Report Traceability by Using Code View Code-to-Model Navigation Model-to-Code Navigation Traceability Report Limitations Web View of Model in Code Generation Report Generate HTML Code Generation Report with Model Web View Model Web View Limitations Generate Code with Annotations or Comments Simulink Annotations Signal Descriptions Text Comments Requirements Comments and Hyperlinks Check Your Model for HDL Compatibility Display Blocks for HDL Code Generation in Library Browser Generate Table of Supported Blocks Trace Code Using the Mapping File Add or Remove the HDL Configuration Component What Is the HDL Configuration Component? Adding the HDL Coder Configuration Component To a Model Removing the HDL Coder Configuration Component From a Model HDL Coding Standards HDL Coding Standard Report Rule Summary Rule Hierarchy Rule and Report Customization How to Fix Warnings and Errors HDL Coding Standards Generate HDL Coding Standard Report from Simulink Using the Configuration Parameters Dialog Box Using the Command Line Basic Coding Practices 1.A General Naming Conventions 1.B General Guidelines for Clocks and Resets 1.C Guidelines for Initial Reset 1.D Guidelines for Clocks 1.F Guidelines for Hierarchical Design RTL Description Rules and Checks 2.A Guidelines for Combinational Logic 2.B Guidelines for “Always” Constructs of Combinational Logic 2.C Guidelines for Flip-Flop Inference 2.D Guidelines for Latch Description 2.E Guidelines for Tristate Buffer 2.F Guidelines for Always/Process Construct with Circuit Structure into Account 2.G Guidelines for “IF” Statement Description 2.H Guidelines for “CASE” Statement Description 2.I Guidelines for “FOR” Statement Description 2.J Guidelines for Operator Description 2.K Guidelines for Finite State Machine Description RTL Design Methodology Guidelines 3.A Guidelines for Creating Function Libraries 3.B Guidelines for Using Function Libraries 3.C Guidelines for Test Facilitation Design Generate HDL Lint Tool Script How to Generate an HDL Lint Tool Script Cascaded Conditional Region Variable Assignments Example Patterns that Fail the Check for Guideline 2.F.B.1.a Example Patterns that Pass the Check for Guideline 2.F.B.1.a Simulink Blocks and Modeling Patterns that Fail the Check for Guideline 2.F.B.1.a Interfacing Subsystems and Models to HDL Code Model Referencing for HDL Code Generation Benefits of Model Referencing for Code Generation How To Generate Code for a Referenced Model Generate Code for Model Arguments Generate Comments Limitations Generate Black Box Interface for Subsystem What Is a Black Box Interface? Requirements Generate a Black Box Interface for a Subsystem Generate Code for a Black Box Subsystem Implementation Generate Black Box Interface for Referenced Model When to Generate a Black Box Interface How to Generate a Black Box Interface Caveats and Limitations Integrate Custom HDL Code by Using DocBlock When to Use DocBlock for Integrating Custom Code Use DocBlock to Integrate Custom Code Restrictions Include Custom HDL Code Using Doc Block Customize Black Box or HDL Cosimulation Interface Interface Parameters Specify Bidirectional Ports Requirements How To Specify a Bidirectional Port Limitations Generate Reusable Code for Subsystems Requirements for Generating Reusable Code for Atomic Subsystems Requirements for Generating Reusable Code for Virtual Subsystems Generate Reusable Code for Atomic Subsystems Generate Reusable Code for Atomic Subsystems with Tunable Mask Parameters Scalarization of Vector Ports in Generated VHDL Code Create a Xilinx System Generator Subsystem Why Use Xilinx System Generator Subsystems Requirements for Xilinx System Generator Subsystems Create a Xilinx System Generator Subsystem Limitations for Code Generation from Xilinx System Generator Subsystems Create an Altera DSP Builder Subsystem Why Use Altera DSP Builder Subsystems? Requirements for Altera DSP Builder Subsystems How to Create an Altera DSP Builder Subsystem Determine Clocking Requirements for Altera DSP Builder Subsystems Limitations for Code Generation from Altera DSP Builder Subsystems Using Altera DSP Builder Advanced Blockset with HDL Coder Using Xilinx System Generator for DSP with HDL Coder Choose a Test Bench for Generated HDL Code Generate a Cosimulation Model Requirements What Is A Cosimulation Model? Generating a Cosimulation Model using the Model Configuration Parameters Structure of the Generated Model Launching a Cosimulation The Cosimulation Script File Complex and Vector Signals in the Generated Cosimulation Model Generating a Cosimulation Model from the Command Line Naming Conventions for Generated Cosimulation Models and Scripts Limitations for Cosimulation Model Generation HDL Verifier Cosimulation Model Generation in HDL Coder Verify HDL Design Using SystemVerilog DPI Test Bench Pass-Through and No-Op Implementations Synchronous Subsystem Behavior with the State Control Block What Is a State Control Block? State Control Block Modes Synchronous Badge for Subsystems by Using Synchronous Mode Generate HDL Code with the State Control Block Using the State Control Block to Generate More Efficient Code with HDL Coder Resettable Subsystem Support in HDL Coder Stateflow HDL Code Generation Support Introduction to Stateflow HDL Code Generation Example Chart Initialization Tunable Parameters Comments in Stateflow Charts Restrictions Hardware Realization of Stateflow Semantics Generate HDL for Mealy and Moore Finite State Machines Generate HDL Code for Moore Finite State Machine Generate HDL for Mealy Finite State Machine Initialize Outputs Every Time Chart Wakes Up Design Patterns Using Advanced Chart Features Temporal Logic Graphical Function Hierarchy and Parallelism Stateless Charts Truth Tables Initialize Persistent Variables in MATLAB Functions MATLAB Function Block with No Direct Feedthrough State Control Block in Synchronous Mode Stateflow Chart Implementing Moore Semantics Generating HDL Code with the MATLAB Function Block HDL Applications for the MATLAB Function Block Structure of Generated HDL Code HDL Applications Viterbi Decoder with the MATLAB Function Block Code Generation from a MATLAB Function Block Counter Model Using the MATLAB Function block Setting Up Creating the Model and Configuring General Model Settings Adding a MATLAB Function Block to the Model Set Fixed-Point Options for the MATLAB Function Block Programming the MATLAB Function Block Constructing and Connecting the DUT_eML_Block Subsystem Compiling the Model and Displaying Port Data Types Simulating the eml_hdl_incrementer_tut Model Generating HDL Code Generate Instantiable Code for Functions How To Generate Instantiable Code for Functions Generate Code Inline for Specific Functions Limitations for Instantiable Code Generation for Functions MATLAB Function Block Design Patterns for HDL HDL Design Pattern Blocks Using Blocks in this Library for HDL Code Generation Fixed-Point Algorithm Support Design Guidelines for the MATLAB Function Block Use Compiled External Functions With MATLAB Function Blocks Build the MATLAB Function Block Code First Use the hdlfimath Utility for Optimized FIMATH Settings Use Optimal Fixed-Point Option Settings Set the Output Data Type of MATLAB Function Blocks Explicitly Using Tunable Parameters Run HDL Model Check for MATLAB Function Blocks Use MATLAB Datapath Architecture for Enhanced HDL Optimizations CORDIC Algorithm Using the MATLAB Function Block Create Hardware Design Patterns Using the MATLAB Function Block For HDL Code Generation Use Distributed Pipelining Optimization in Models with MATLAB Function Blocks Generating Scripts for HDL Simulators and Synthesis Tools Generate Scripts for Compilation, Simulation, and Synthesis Structure of Generated Script Files Properties for Controlling Script Generation Enabling and Disabling Script Generation Customizing Script Names Customizing Script Code Examples Configure Compilation, Simulation, Synthesis, and Lint Scripts Compilation Script Options Simulation Script Options Synthesis Script Options Lint Script Options Add Synthesis Attributes Configure Synthesis Project Using Tcl Script Using the HDL Workflow Advisor Workflows in HDL Workflow Advisor Set Up HDL Workflow Advisor in MATLAB Set Up HDL Workflow Advisor in Simulink Generic ASIC/FPGA FPGA Turnkey IP Core Generation Simulink Real-Time FPGA I/O FPGA-in-the-Loop Getting Started with the HDL Workflow Advisor Open the HDL Workflow Advisor Run Tasks in the HDL Workflow Advisor Fix HDL Workflow Advisor Warnings or Failures Save and Restore the HDL Workflow Advisor State View and Save HDL Workflow Advisor Reports Generate Code and Synthesize on FPGA Using HDL Workflow Advisor FIR Filter Model Create a Folder and Copy Relevant Files Set Up Tool Path Open the HDL Workflow Advisor Generate HDL Code and Synthesize on FPGA Run Workflow at Command Line with a Script Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor Generate HDL Code for Vendor-Specific FPGA Floating-Point Target Libraries Set Up Design for Mixed-Mode Mapping Map to Native Floating-Point and FPGA Floating-Point Libraries View Code Generation Reports of Floating-Point Library Mapping Analyze Results of Floating-Point Library Mapping FPGA Floating-Point Library IP Mapping Customize Floating-Point IP Configuration Customize the IP Latency with Target Frequency Customize the IP Latency with Latency Strategy HDL Coder Support for FPGA Floating-Point Library Mapping Supported Blocks That Map to FPGA Floating-Point Target IP Supported Blocks That Do Not Need to Map to FPGA Floating-Point Target IP Limitations for FPGA Floating-Point Library Mapping Synthesis Objective to Tcl Command Mapping Altera Quartus II Xilinx Vivado 2014.4 Xilinx ISE 14.7 with PlanAhead Run HDL Workflow with a Script Export an HDL Workflow Script Specify Verbosity of Workflow Script Enable or Disable Tasks in HDL Workflow Script Run a Single Workflow Task Import an HDL Workflow Script Generic ASIC/FPGA Workflow Script Example FPGA-in-the-Loop Script Example FPGA Turnkey Workflow Script Example IP Core Generation Workflow Script Example Simulink Real-Time FPGA I/O Workflow Example Get Started with HDL Workflow Command-Line Interface Getting Started with FPGA Turnkey Workflow Simscape to HDL Workflow Get Started with Simscape Hardware-in-the-Loop Workflow Modeling Physical Systems in Simscape for HDL Compatibility Simscape Example Models for HDL Code Generation Generate HDL Implementation Model by Using the Simscape HDL Workflow Advisor HDL Code Generation and Deployment Restrictions for HDL Code Generation from Simscape Models Modeling Guidelines for Simscape Subsystem Replacement Enclose Simscape Blocks Inside a Subsystem Multiple Simscape Network Considerations Avoid Using Certain Blocks in Simscape Utilities Library Generate HDL Code for Simscape Models Generate Optimized HDL Implementation Model from Simscape Generate Simulink Real-Time Interface Subsystem for Simscape Two-Level Converter Model Deploy Simscape Buck Converter Model to Speedgoat IO Module Using HDL Workflow Script Deploy Simscape Grid Tied Converter Model to Speedgoat IO Module Using HDL Workflow Script Partition Simscape Models Containing a Large Network into Multiple Smaller Networks Generate HDL Code for Simscape Models with Multiple Networks Replace Piecewise-Constant Resistor with Switched Linear Components Hardware-in-the-Loop Implementation of Simscape Model on Speedgoat FPGA I/O Modules Validate HDL Implementation Model to Simscape Algorithm Bridge Rectifier Model Increase Validation Logic Tolerance Increase Number of Solver Iterations Use Larger Floating-Point Precision Improve Sampling Rate of HDL Implementation Model Generated from Simscape Algorithm Sampling Frequency Boost Converter Model Reducing Number of Solver Iterations Using Oversampling Factor and Latency Strategy Generate HDL Code for Nonlinear Simscape Models by Using Partitioning Solver Deploy Simscape DC Motor Model to Speedgoat FPGA IO Module Generate HDL Code for Simscape Three-Phase PMSM Drive Containing Averaged Switch Generate HDL Code for Two-Speed Transmission Model Containing Mode Charts Simscape Language Support Domain and Component Declarations Equations Discrete Events and Mode Charts Composite Components Generate HDL Code for Simscape Models by Using Trapezoidal Rule Solver Simscape HDL Workflow Advisor Tasks Simscape HDL Workflow Advisor Tasks Simscape HDL Workflow Advisor Code Generation Compatibility Check Solver Configuration Check Model Compatibility State-Space Conversion Extract Equations Discretize Equations Implementation Model Generation Set Target and Frequency Generate Implementation Model Simscape HDL Workflow Advisor Tips and Guidelines Estimating Resource Consumption Using Algebraic and Differential Variables Setting Simulation Stop Time for Extracting Equations Changing Sample Time for Discretizing Equations Using Number of Solver Iterations Floating-Point Precision and Numerical Accuracy Map State Space Parameters to RAMs Troubleshooting Troubleshooting Real-Time Hardware Deployment Issues in Simscape Hardware-in-the-Loop Workflow Parameter Settings Critical Path Estimation How Sample Rate Affects the Timing on the Hardware How to Reduce the Sample Rate Variation Limitations Model Protection in HDL Coder Create Protected Models to Conceal Contents and Generate HDL Code How Model Protection Works How to Create a Protected Model General Protected Model Requirements and Limitations Protected Model Restrictions for HDL Code Generation Prepare the Parent Model Protect the Referenced Model Protected Model Report Generate HDL Code for Models Referencing Protected Model Test Protected Models Package and Share Protected Models Harness Model MAT-File with Base Workspace Definitions Simulink Data Dictionary Protected Model File Contents Obfuscate Generated HDL Code from Simulink Models How to Generate Obfuscated HDL Code Generated HDL Code with Obfuscation Code Obfuscation Report HDL Model Parameters Incompatible with Code Obfuscation Code Obfuscation Considerations and Restrictions HDL Test Bench Verify Generated Code Using HDL Test Bench from Configuration Parameters FIR Filter Model Create a Folder and Copy Relevant Files What is a HDL Test Bench? How to Verify the Generated Code Generate HDL Test Bench View HDL Test Bench Files Run Simulation and Verify Generated HDL Code Verify Generated Code Using HDL Test Bench at Command Line FIR Filter Model Create a Folder and Copy Relevant Files What is a HDL Test Bench? How to Verify the Generated Code Generate HDL Test Bench View HDL Test Bench Files Run Simulation and Verify Generated HDL Code Test Bench Generation How Test Bench Generation Works Test Bench Data Files Test Bench Data Type Limitations Use Constants Instead of File I/O Test Bench Block Restrictions FPGA Board Customization FPGA Board Customization Feature Description Custom Board Management FPGA Board Requirements Create Custom FPGA Board Definition Create Xilinx KC705 Evaluation Board Definition File Overview What You Need to Know Before Starting Start New FPGA Board Wizard Provide Basic Board Information Specify FPGA Interface Information Enter FPGA Pin Numbers Run Optional Validation Tests Save Board Definition File Use New FPGA Board FPGA Board Manager Introduction Filter Search FIL Enabled/Turnkey Enabled Create Custom Board Add Board from File Get More Boards View/Edit Remove Clone Validate New FPGA Board Wizard Basic Information Interfaces FIL I/O Turnkey I/O Validation Finish FPGA Board Editor General Tab Interface Tab HDL Workflow Advisor Tasks HDL Workflow Advisor Tasks HDL Workflow Advisor Tasks Overview Set Target Overview Set Target Device and Synthesis Tool Set Target Reference Design Set Target Interface Set Target Interface Set Target Frequency Prepare Model for HDL Code Generation Overview Check Model Settings Check FPGA-in-the-Loop Compatibility HDL Code Generation Overview Set HDL Options Generate RTL Code and Testbench Verify with HDL Cosimulation Generate RTL Code and IP Core FPGA Synthesis and Analysis Overview Create Project Perform Synthesis and P/R Overview Perform Logic Synthesis Perform Mapping Perform Place and Route Run Synthesis Run Implementation Annotate Model with Synthesis Result Download to Target Overview Generate Programming File Program Target Device Generate Simulink Real-Time Interface Save and Restore HDL Workflow Advisor State FPGA-in-the-Loop (FIL) Implementation Set FPGA-in-the-Loop Options Build FPGA-in-the-Loop Embedded System Integration Create Project Generate Software Interface Build FPGA Bitstream Program Target Device HDL Code Advisor HDL Coder Checks in Model Advisor / HDL Code Advisor Overview Model configuration checks overview Check for model parameters suited for HDL code generation Description Results and Recommended Actions See Also Check for global reset setting for Xilinx and Altera devices Description Results and Recommended Actions See Also Check inline configurations setting Description Results and Recommended Actions Check algebraic loops Description Results and Recommended Actions See Also Check for visualization settings Description Results and Recommended Actions See Also Check delay balancing setting Description Results and Recommended Actions See Also Check for ports and subsystems overview Check for invalid top level subsystem Description Results and Recommended Actions Check for blocks and block settings overview Check for infinite and continuous sample time sources Description Results and Recommended Actions See Also Check for unsupported blocks Description Results and Recommended Actions Check for large matrix operations Description Results and Recommended Actions See Also Check for MATLAB Function block settings Description Results and Recommended Actions See Also Check for Stateflow chart settings Description Results and Recommended Actions See Also Check for obsolete Unit Delay Enabled/Resettable Blocks Description Results and Recommended Actions Check for blocks that have nonzero output latency Description Results and Recommended Actions See Also Check for unsupported storage class for signal objects Description Results and Recommended Actions Check for HDL Reciprocal block usage Description Results and Recommended Actions See Also Check for Trigonometric Function block for LUT-based approximation method Description Results and Recommended Actions Capabilities and Limitations See Also Native Floating Point Checks Overview Check for single datatypes in the model Description Results and Recommended Actions See Also Check for double data types in the model Description Results and Recommended Actions See Also Check for Data Type Conversion blocks with incompatible settings Description Results and Recommended Actions See Also Check for HDL Reciprocal block usage Description Results and Recommended Actions See Also Check for Relational Operator block usage Description Results and Recommended Actions See Also Check for unsupported blocks with Native Floating Point Description Results and Recommended Actions See Also Check blocks with nonzero ULP error Description Results and Recommended Actions See Also Industry standard checks overview Check file extension Description Results and Recommended Actions See Also Check naming conventions Description Results and Recommended Actions See Also Check top-level subsystem/port names Description Results and Recommended Actions See Also Check module/entity names Description Results and Recommended Actions See Also Check signal and port names Description Results and Recommended Actions See Also Check package file names Description Results and Recommended Actions See Also Check generics Description Results and Recommended Actions See Also Check clock, reset, and enable signals Description Results and Recommended Actions See Also Check architecture name Description Results and Recommended Actions See Also Check entity and architecture Description Results and Recommended Actions See Also Check clock settings Description Results and Recommended Actions See Also Using the HDL Code Advisor Check HDL Compatibility of Simulink Model Using HDL Code Advisor Open the HDL Code Advisor Run Checks In the HDL Code Advisor Fix HDL Code Advisor Warnings or Failures View and Save HDL Code Advisor Reports Run Model Advisor Checks for HDL Coder Open the Model Advisor Checks Run Checks in the Model Advisor Display Check Results in the Model Advisor Report Fix Warnings or Failures HDL Code Advisor Checks Model configuration checks Checks for ports and subsystems Checks for blocks and block settings Native Floating Point checks industry standard checks Hardware-Software Codesign Hardware-Software Co-Design Basics Targeting FPGA & SoC Hardware Overview Hardware-Software Co-Design Prototype and Deploy HDL Algorithm for an FPGA Deploy C Algorithm for Processor Create Custom Hardware Platform Hardware-Software Co-Design Workflow for SoC Platforms Speedgoat FPGA Support with HDL Workflow Advisor Speedgoat Simulink-Programmable I/O Module Support Prepare for FPGA Workflow Custom IP Core Generation Custom IP Core Architectures Target Platform Interfaces Processor and FPGA Synchronization Custom IP Core Generated Files Restrictions Custom IP Core Report Summary Target Interface Configuration Register Address Mapping Bit Packing Order IP Core User Guide IP Core File List Generate Board-Independent HDL IP Core from Simulink Model Generate Board-Independent IP Core Generate Tool-Independent IP Core IP Core Without AXI4 Slave Interfaces Requirements and Limitations for IP Core Generation Processor and FPGA Synchronization Free Running Mode Coprocessing – Blocking Mode Synchronization of Global Reset Signal to IP Core Clock Domain IP Caching for Faster Reference Design Synthesis Requirements for Using IP Caching What Is an IP Cache? How IP Caching Works Enable IP Caching IP Caching in HDL Coder Reference Designs IP Caching in Custom Reference Designs Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows Step 1: Identify the Timing Failure Step 2: Find the Critical Path Step 3: Resolve Timing Failures Define Multiple AXI Master Interfaces in Reference Designs to Access DUT AXI4 Slave Interface Vivado-Based Reference Designs Qsys-Based Reference Designs Program Target FPGA Boards or SoC Devices How to Program Target Device Programming Methods Generate Host Interface Script to Probe and Rapidly Prototype HDL IP Core Prerequisites Generate Software Interface Host Interface Script Generate Software Interface Model to Probe and Rapidly Prototype HDL IP Core Prerequisites Generate Software Interface Software Interface Model Create Host Interface Script to Control and Rapidly Prototype HDL IP Core Prerequisites Ethernet-Based Interface JTAG-Based Interface Getting Started with Targeting Xilinx Zynq Platform Getting Started with Targeting Zynq UltraScale+ MPSoC Platform Getting Started with Targeting Intel SoC Devices Getting Started with Targeting Intel Quartus Pro Based Devices Integrate HDL IP Core with Microchip PolarFire SoC Icicle Kit Reference Design Save Target Hardware Settings in Model Generate IP Core from MATLAB for Blinking LED on FPGA Board Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow IP Core Generation Workflow with a MicroBlaze processor: Xilinx Kintex-7 KC705 Map Bus Data types to AXI4 Slave Interfaces Prototype FPGA Design on Hardware with Live Data by Using MATLAB Commands Author a Xilinx Zynq Linux Image for a Custom Zynq Board by Using MathWorks Buildroot Generate Board-Independent HDL IP Core for Microchip Platforms Getting Started with Targeting Xilinx Versal ACAP Platform Target SoC Platforms and Speedgoat Boards Model Design for AXI4 Slave Interface Generation Considerations Map Scalar Ports to AXI4 Slave Interface Map Vector Ports to AXI4 Slave Interface Map Double Data Types and Data Larger than 32 bits to AXI4-Slave Interfaces Map Bus Data Types to AXI4 Slave Interface Specify Initial Value of AXI4 Slave Registers Read Back Value of AXI4 Slave Interfaces Optimize AXI4 Slave Read Logic Model Design for AXI4-Stream Interface Generation Sample-Based Modeling Frame-Based Modeling Legacy Frame-Based Modeling Model Designs with Multiple Streaming Channels Model Designs That Have Multiple Sample Rates Interface Options for AXI4-Stream Data Restrictions Model Design for Frame-Based IP Core Generation Frame-Based Modeling for AXI4-Stream Interfaces Frame-Based Modeling for AXI4-Stream Video Interfaces Enable the Optimization Modeling Requirements Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces Why Use Multiple AXI4 Interfaces Specify Multiple AXI4 Interfaces in Generic IP Core Generation Workflow Specify Multiple AXI4 Interfaces in Custom Reference Designs Ready Signal Mapping for Multiple Streaming Interfaces Restrictions Running Audio Filter with Multiple AXI4-Stream Channels on ZedBoard Inspect the Written Values of AXI4 Slave Registers by Using the Readback Methods Multirate IP Core Generation Board and Reference Design Registration System Board, IP Core, and Reference Design Definitions Board Registration Files Reference Design Registration Files Predefined Board and Reference Design Examples Register a Custom Board Define a Board Create a Board Plugin Define a Board Registration Function Register a Custom Reference Design Define a Reference Design Create a Reference Design Plugin Define a Reference Design Registration Function Define Custom Parameters and Callback Functions for Custom Reference Design Define Custom Parameters and Register Callback Function Handle Define Custom Callback Functions Customize Reference Design Dynamically Based on Reference Design Parameters Why Customize the Reference Design How Reference Design Customization Works Customizable Reference Design Parameters Example: Create Master Only or Slave Only or Both Slave and Master Reference Designs Define and Add IP Repository to Custom Reference Design Create an IP Repository Folder Structure Define IP List Function Add IP List Function to Reference Design Project FPGA Programming and Configuration on Speedgoat Simulink-Programmable I/O Modules Model Design for AXI4-Stream Video Interface Generation Sample Based Modeling Protocol Signals and Timing Diagrams Model Data and Control Bus Signals Map DUT Ports to Multiple Channels Model Designs with Multiple Sample Rates Video Porch Insertion Logic Default Video System Reference Design Restrictions Frame-Based Modeling Model Design for AXI4 Master Interface Generation Simplified AXI4 Master Protocol - Write Channel Simplified AXI4 Master Protocol - Read Channel Base Address Register Calculation Specify Initial Value of AXI4 Master Read and Write Base Address Modeling for AXI4 Master Interfaces Map Vector Ports to AXI4 Master Interfaces Model ID Signals to Reduce the Number of AXI-4 Master Interfaces Model Designs with Multiple Sample Rates Reference Designs for IP Core Integration Restrictions IP Core Generation Workflow for Standalone FPGA Devices Targeting FPGA Reference Designs with AXI4 Interface Targeting FPGA Reference Designs Without AXI4 Interface Board Support Restrictions IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules Supported I/O Modules IP Core Generation Workflow Restrictions Map Bus Data Types to PCIe Interface Model Bus Element IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip Running an Audio Filter on Live Audio Input Using Intel Board Running an Audio Filter on Live Audio Input Using a Zynq Board Deploy Model with AXI-Stream Interface in Zynq Workflow Deploy Model with AXI4-Stream Video Interface in Zynq Workflow Perform Matrix Operation Using External Memory Authoring a Reference Design for Audio System on a Zynq Board Authoring a Reference Design for Audio System on a ZYBO Board Authoring a Reference Design for Audio System on Intel Board Define Custom Board and Reference Design for Zynq Workflow Define Custom Board and Reference Design for Intel SoC Workflow Define Custom Board and Reference Design for Microchip Workflow Define Custom Board and Reference Design for Microchip Pure FPGA Platforms Dynamically Create Reference Design with Master Only or Slave Only AXI4-Stream Interface Use JTAG AXI Manager to Control HDL Coder Generated IP Core Debug a Zynq Design Using HDL Coder and Embedded Coder Debug IP Core Using FPGA Data Capture Field-Oriented Control of a Permanent Magnet Synchronous Machine on a Xilinx Zynq Platform Deploy a Frame-Based Model with AXI4-Stream Interfaces Deploy Frame-Based Models with AXI4-Stream Video Interfaces in Zynq-Based Hardware DAC and ADC Loopback Data Capture IQ Mixer Mode Capture PL-DDR4 ADC Data Capture DAC PL-DDR4 Transmit Polyphase Channelizer Multi-Tile Synchronization Device Tree Generation Generate Device Tree for IP Core Get Started with Device Trees Use Device Trees with IP Core Generation Workflow Deploy Device Tree and Bitstream Sample Device Tree